參數(shù)資料
型號(hào)： CYP15G0403DXB-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, BGA-256
文件頁(yè)數(shù)： 23/45頁(yè)
文件大小： 517K
代理商： CYP15G0403DXB-BGI
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 23 of 45
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets all four channels. Initialize the JTAG state machine
to its reset state as detailed in
“JTAG Support” on page 24
.
2. Set the static receiver latch bank for the target channel. May
be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
3. Set the static transmitter latch bank for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional step if the default settings match
the desired configuration.]
4. Set the dynamic bank of latches for the target channel.
Enable the Receive PLLs and transmit channels. May be
performed using a global operation, if the application
permits it. [Required step.]
5. Reset the Phase Alignment Buffer for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional if phase align buffer is
bypassed.]
When a receive channel is configured with the decoder
bypassed and the receive clock selected as recovered clock
in half-rate mode (DECBYPx = 0, RXRATEx = 1, RXCKSELx
= 0), the channel cannot be dynamically reconfigured to
enable the decoder with RXCLKx selected as the REFCLKx
(DECBYPx = 1, RXCKSELx = 1). If such a change is desired,
a global reset should be performed and all channels should be
reconfigured to the desired settings.
GLEN[11..0]
Global Enable
. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx
= 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable
. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal
ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel,
FGLEN forces the global update of the target latch banks.
FGLEN[2..0]
Table 9. Device Configuration and Control Latch Descriptions
(continued)
Name
Signal Description
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP15G0403DXB-BGXC 功能描述:電信線路管理 IC Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0403DXB-BGXI 功能描述:電信線路管理 IC Ind. Clock Quad HOTLink II Xcvr RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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