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參數(shù)資料
| 型號(hào)： | CYM9270 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 36 SRAM Module(64K x 36 靜態(tài)RAM模塊) |
| 中文描述： | 64K的× 36的SRAM模塊（64K的× 36靜態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | CYM9270 |
CYM9270
CYM9271B
CYM9272A
CYM9273
7
AC Test Loads and Waveforms
[3]
3.3V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
OUTPUT
R1
R2
5 pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
ALL INPUT PULSES
OUTPUT
R
L
= 50
V
L
= 1.5V
V
CCQ
[2]
Switching Characteristics
Over the Operating Range
Parameter
Description
CYM9270
Min.
CYM9271B
Min.
CYM9272A
Min.
CYM9273
Min.
Max.
Max.
Max.
Max.
Unit
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
WES
t
WEH
t
DS
t
DH
t
CSS
t
CSH
t
EOZ[4]
t
EOV
Notes:
2.
3.
Clock Cycle Time
12
12
12
12
ns
Clock HIGH
4
4
4
4
ns
Clock LOW
4
4
4
4
ns
Address Set-Up Before CLK Rise
3
3
3
3
ns
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Data Output Valid After CLK Rise
10.3
10.3
10.3
10.3
ns
Data Output Hold After CLK Rise
3
3
3
3
ns
WH, WL Set-Up Before CLK Rise
3.1
3.1
3.1
3.1
ns
WH, WL Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Data Input Set-Up Before CLK Rise
3.3
3.3
3.3
3.3
ns
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
Chip Select Set-Up
3.1
3.1
3.1
3.1
ns
Chip Select Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
OE HIGH to Output High Z
7
7
7
7
ns
OE LOW to Output Valid
7
7
7
7
ns
Resistor values for V
=3.3V are R1=317
and R2=351
.
Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
/I
and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are at room temperature.
t
EOZ
is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
4.
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