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參數(shù)資料
| 型號(hào)： | CYM1861V33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2,048K x 32 3.3V Static RAM Module(2048K x 32 3.3V 靜態(tài)RAM模塊) |
| 中文描述： | 2,048畝× 32 3.3靜態(tài)存儲(chǔ)器模塊（2048K × 32 3.3靜態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | CYM1861V33 |
CYM1861V33
PRELIMINARY
3
AC Test Loads and Waveforms
1861V33
–
3
1861V33
–
4
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 589
R1 589
R2
434
R2
434
250
Equivalent to:
TH
é
VENIN
EQUIVALENT
1.40V
Switching Characteristics
Over the Operating Range
[3]
1861V33-20
1861V33-25
Parameter
READ CYCLE
Description
Min.
Max.
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
4.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
5.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
6.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
20
25
ns
Address to Data Valid
20
25
ns
Data Hold from Address Change
3
3
ns
CS LOW to Data Valid
20
25
ns
OE LOW to Data Valid
12
15
ns
OE LOW to Low Z
0
4
ns
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
10
12
ns
3
7
ns
10
12
ns
CS HIGH to Power-Down
20
25
ns
Write Cycle Time
20
25
ns
CS LOW to Write End
17
20
ns
Address Set-Up to Write End
17
20
ns
Address Hold from Write End
3
3
ns
Address Set-Up to Write Start
2
2
ns
WE Pulse Width
15
20
ns
Data Set-Up to Write End
12
15
ns
Data Hold from Write End
2
2
ns
WE HIGH to Low Z
WE LOW to High Z
[5]
3
3
ns
0
12
0
12
ns
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