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參數(shù)資料
| 型號： | CYM1861 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2,048K x 32 Static RAM Module(2048K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 2,048畝× 32靜態(tài)RAM模塊（2048K × 32靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 105K |
| 代理商： | CYM1861 |
PRELIMINARY
2,048K x 32 Static RAM Module
CYM1861
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
May 4, 1998
Features
High-density 64-megabit SRAM module
32-bit Standard Footprint supports densities from 16K
x 32 through 2M x 32
High-speed SRAMs
—Access time of 35 ns
72 pins
Available in SIMM format
Functional Description
The CYM1861 is a high-performance 64-megabit static RAM
module organized as 2,048K words by 32 bits. This module is
constructed from sixteen 1,024K x 4 SRAMs in SOJ packages
mounted on an epoxy laminate substrate. Four chip selects are
LogicBlockDiagram
used to independently enable the four bytes. Reading or writ-
ing can be executed on individual bytes or any combination of
multiple bytes through proper use of selects.
The CYM1861 is designed for use with standard 72-pin SIMM
sockets. The pinout is downward compatible with the 64-pin
JEDEC SIMM module family (CYM1821, CYM1831,
CYM1836, and CYM1841). Thus, a single motherboard de-
sign can be used to accommodate memory depth ranging from
16K words (CYM1821) to 2,048K words (CYM1861). The
CYM1861 is offered in vertical SIMM configuration and is avail-
able with tin-lead edge contacts.
Presence detect pins (PD
0
–PD
3
) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Pin Configuration
1861–1
A
0
–A
19
1861–2
OE
WE
I/O
0
–I/O
3
CS
1
20
4
–CS
4
PD
0
- OPEN
PD
1
- GND
PD
2
- GND
PD
3
- OPEN
1M x 4
SRAM
ZIP/SIMM
Top View
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
7
A
8
A
9
I/O
4
I/O
5
A
4
A
5
PD
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
6
I/O
7
WE
A
14
CS
1
GND
A
15
CS
2
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
A
19
NC
I/O
14
I/O
15
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
A
20
A
20
Buffer
PAL
I/O
4
–I/O
7
4
I/O
8
–I/O
11
4
1M x 4
SRAM
I/O
12
I/O
15
4
I/O
16
I/O
19
–
4
1M x 4
SRAM
I/O
20
I/O
23
–
4
I/O
24
I/O
27
–
4
1M x 4
SRAM
I/O
28
I/O
31
–
4
–
I/O
0
–I/O
3
4
1M x 4
SRAM
I/O
4
–I/O
7
4
I/O
8
–I/O
11
4
1M x 4
SRAM
I/O
12
I/O
15
4
I/O
16
I/O
19
–
4
1M x 4
SRAM
I/O
20
I/O
23
–
4
I/O
24
I/O
27
–
4
1M x 4
SRAM
I/O
28
I/O
31
–
4
–
Selection Guide
1861-25
25
1200
480
1861-35
35
960
480
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains advance information.
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