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參數(shù)資料
| 型號： | CYM1851V33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1,024K x 32 3.3V Static RAM Module(1024K x 32 3.3V 靜態(tài)RAM模塊) |
| 中文描述： | 1024畝× 32 3.3靜態(tài)存儲器模塊（1024K × 32 3.3靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 122K |
| 代理商： | CYM1851V33 |
CYM1851V33
PRELIMINARY
3
AC Test Loads and Waveforms
1851V33
–
3
1851V33
–
4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≥
5 ns
≥
5 ns
OUTPUT
R1 317
R1 317
R2
351
R2
351
167
Equivalent to:
TH
é
VENIN
EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[3]
1851V33-12
1851V33-15
Parameter
READ CYCLE
Description
Min.
Max.
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
12
15
ns
Address to Data Valid
12
15
ns
Data Hold from Address Change
3
3
ns
CS LOW to Data Valid
12
15
ns
OE LOW to Data Valid
7
8
ns
OE LOW to Low Z
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
7
8
ns
3
3
ns
7
8
ns
CS HIGH to Power-Down
12
15
ns
Write Cycle Time
12
15
ns
CS LOW to Write End
9
10
ns
Address Set-Up to Write End
9
10
ns
Address Hold from Write End
0
0
ns
Address Set-Up to Write Start
1
1
ns
WE Pulse Width
10
12
ns
Data Set-Up to Write End
7
8
ns
Data Hold from Write End
1
1
ns
WE HIGH to Low Z
WE LOW to High Z
[5]
3
3
ns
0
7
0
8
ns
Shaded area contains advance information.
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