參數(shù)資料
型號: CYM1846
廠商: Cypress Semiconductor Corp.
英文描述: 512K x 32 Static RAM Module(512K x 32 位靜態(tài)模塊)
中文描述: 512k × 32的靜態(tài)RAM模塊(512k × 32的位靜態(tài)模塊)
文件頁數(shù): 4/7頁
文件大小: 136K
代理商: CYM1846
CYM1846
4
Switching Characteristics
Over the Operating Range
[3]
(continued)
1846–20
1846–25
1846–35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
Read Cycle Time
20
25
35
ns
Address to Data Valid
20
25
35
ns
Data Hold from Address Change
3
3
3
ns
CS LOW to Data Valid
20
25
35
ns
OE LOW to Data Valid
10
15
25
ns
OE LOW to Low Z
0
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
10
12
12
ns
3
3
3
ns
10
12
12
ns
CS HIGH to Power-Down
20
25
35
ns
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
20
25
35
ns
CS LOW to Write End
15
20
30
ns
Address Set-Up to Write End
15
20
30
ns
Address Hold from Write End
0
0
0
ns
Address Set-Up to Write Start
1
2
2
ns
WE Pulse Width
15
20
30
ns
Data Set-Up to Write End
10
15
20
ns
Data Hold from Write End
1
2
2
ns
WE HIGH to Low Z
WE LOW to High Z
[6]
3
4
5
ns
0
10
0
12
0
12
ns
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4.
5.
6.
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