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參數(shù)資料
| 型號： | CYM1831PZ-20C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 Static RAM Module |
| 中文描述： | 64K X 32 MULTI DEVICE SRAM MODULE, 20 ns, PZMA64 |
| 封裝： | PLASTIC, ZIP-64 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 246K |
| 代理商： | CYM1831PZ-20C |
CYM1831
Document #: 38-05270 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[3]
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
Description
1831-15
Min.
1831-20
Min.
1831-25
Min.
1831-30
Min.
1831-35
Min.
1831-45
Min.
Unit
Max.
Max.
Max.
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from
Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE LOW to High Z
CS LOW to Low Z
[4]
15
20
25
30
35
45
ns
ns
ns
15
20
25
30
35
45
3
3
3
3
3
3
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
15
8
20
10
25
15
30
20
35
20
45
30
ns
ns
ns
ns
ns
0
0
0
0
0
0
8
10
15
15
20
20
0
0
3
3
3
3
t
HZCS
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
CS HIGH to High Z
[4, 5]
6
8
13
15
20
20
ns
Write Cycle Time
CS LOW to Write End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to Write
End
Data Hold from Write
End
WE HIGH to Low Z
WE LOW to High Z
[5]
15
10
10
20
15
15
25
20
20
30
25
25
35
30
30
45
40
40
ns
ns
ns
t
HA
2
2
2
2
2
2
ns
t
SA
2
2
2
2
2
2
ns
t
PWE
t
SD
10
8
15
12
20
15
25
15
25
20
30
20
ns
ns
t
HD
2
2
2
2
2
2
ns
t
LZWE
t
HZWE
Note:
3.
3
0
3
0
3
0
3
0
3
0
3
0
ns
ns
7
10
13
15
20
20
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4.
5.
6.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 481
R1 481
R2
255
R2
255
167
Equivalent to:
TH
é
VENIN EQUIVALENT
1.73V
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYM1831PZ-25C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 32 Static RAM Module |
| CYM1831PZ-35C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 32 Static RAM Module |
| CYM1831PZ-45C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 32 Static RAM Module |
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| CYM1831V33PZ-35C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
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