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參數(shù)資料
| 型號： | CYM1821 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x 32 Static RAM Module(16K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 16K的× 32靜態(tài)RAM模塊（16K的× 32靜態(tài)RAM的模塊） |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 114K |
| 代理商： | CYM1821 |
DS1821
062498 8/15
The bus master transmits (TX) a reset pulse (a low sig-
nal for a minimum of 480
μ
s). The bus master then
releases the line and goes into a receive mode (RX).
The 1–Wire bus is pulled to a high state via the 5K
pull–up resistor . After detecting the rising edge on the
DQ pin, the DS1821 waits 15–60
μ
s and then transmits
the presence pulse (a low signal for 60–240
μ
s).
READ/WRITE TIME SLOTS
DS1821 data is read and written through the use of time
slots to manipulate bits and a command word to specify
the transaction.
Write Time Slots
A write time slot is initiated when the host pulls the data
line from a high logic level to a low logic level. There are
two types of write time slots: Write One time slots and
Write Zero time slots. All write time slots must be a mini-
mum of 60
μ
s in duration with a minimum of a one
μ
s
recovery time between individual write cycles.
The DS1821 samples the DQ line in a window of 15
μ
s to
60
μ
s after the DQ line falls. If the line is high, a Write
One occurs. If the line is low, a Write Zero occurs (see
Figure 6).
For the host to generate a Write One time slot, the data
line must be pulled to a logic low level and then released,
allowing the data line to pull up to a high level within 15
microseconds after the start of the write time slot.
For the host to generate a Write Zero time slot, the data
line must be pulled to a logic low level and remain low for
the duration of the write time slot.
Read Time Slots
The host generates read time slots when data is to be
read from the DS1821. A read time slot is initiated when
the host pulls the data line from a logic high level to logic
low level. The data line must remain at a low logic level
for a minimum of one
μ
s microsecond; output data from
the DS1821 is then valid for the next 14
μ
s maximum.
The host therefore must stop driving the DQ pin low in
order to read its state 15
μ
s from the start of the read slot
(see Figure 6). By the end of the read time slot, the DQ
pin will pull back high via the external pull–up resistor. All
read time slots must be a minimum of 60
μ
s in duration
with a minimum of a one
μ
s recovery time between indi-
vidual read slots.
Figure 7 shows that the sum of T
INIT
, T
RC
, and T
SAMPLE
must be less than 15
μ
s. Figure 8 shows that system tim-
ing margin is maximized by keeping T
INIT
and T
RC
as
small as possible and by locating the master sample
time towards the end of the 15
μ
s period.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 5
MASTER T
X
“RESET PULSE”
480
μ
s MINIMUM
960
μ
s MAXIMUM
MASTER R
480
μ
s MINIMUM
V
CC
GND
DS1821
WAITS
15 – 60
μ
s
DS1821 T
“PRESENCE PULSE”
60 – 240
μ
s
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
BOTH BUS MASTER
AND DS1821 ACTIVE
LOW
DS1821 ACTIVE LOW
RESISTOR PULL–UP
1–WIRE
BUS
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