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參數(shù)資料
| 型號(hào)： | CYM1821 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x 32 Static RAM Module(16K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 16K的× 32靜態(tài)RAM模塊（16K的× 32靜態(tài)RAM的模塊） |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | CYM1821 |
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DS1821
062498 7/15
1–WIRE BUS SYSTEM
The DS1821 1–Wire bus is a system which has a single
bus master and one slave. The DS1821 behaves as a
slave. The DS1821 is not able to be multidropped,
unlike other 1–Wire devices from Dallas Semi–
conductor.
The discussion of this bus system is broken down into
three topics: hardware configuration, transaction
sequence, and 1–Wire signaling (signal types and
timing).
HARDWARE CONFIGURATION
The 1–Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1–Wire bus must have open drain or
3–state outputs. The 1–Wire port of the DS1821 (DQ
pin) is open drain with an internal circuit equivalent to
that shown in Figure 4. The 1–Wire bus requires a
pull–up resistor of approximately 5K.
HARDWARE CONFIGURATION
Figure 4
+5V
R
X
T
X
100 OHM
MOSFET
4.7K
R
X
T
X
5
μ
A
Typ.
BUS MASTER
DS1821 1–WIRE PORT
R
X
= RECEIVE
T
X
= TRANSMIT
The idle state for the 1–Wire bus is high. If for any reason
a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. Infinite
recovery time can occur between bits so long as the
1–Wire bus is in the inactive (high) state during the re-
covery period. If this does not occur and the bus is left
low for more than 480
μ
s, all components on the bus will
be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS1821 via the 1–Wire
port is as follows:
Initialization
Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1–Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS1821 is on the bus and is ready to operate. For more
details, see the “1–Wire Signaling” section.
1–WIRE SIGNALING
The DS1821 requires strict protocols to insure data
integrity. The protocol consists of several types of
signaling on one line: reset pulse, presence pulse, write
0, write 1, read 0, and read 1. All of these signals, with
the exception of the presence pulse, are initiated by the
bus master.
The initialization sequence required to begin any com-
munication with the DS1821 is shown in Figure 5. A
reset pulse followed by a presence pulse indicates the
DS1821 is ready to send or receive data given the cor-
rect function command.
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