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參數(shù)資料
| 型號(hào)： | CYK256K16MCCBU-70BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Pseudo Static RAM |
| 中文描述： | 256K X 16 PSEUDO STATIC RAM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, FBGA-48 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | CYK256K16MCCBU-70BVI |
4-Mbit (256K x 16) Pseudo Static RAM
CYK256K16MCCB
MoBL3
Cypress Semiconductor Corporation
Document #: 38-05585 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised October 18, 2006
Features
Wide voltage range: 2.70V–3.30V
Access time: 55 ns, 60 ns and 70 ns
Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f
max
(70-ns speed)
Ultra low standby power
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in a 48-ball BGA package
Functional Description
[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/O
7
) is written into the location specified on the address pins
(A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE
LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. Refer to the truth table for a complete description of read
and write modes.
Note:
1. For best practice recommendations, please refer to the CY application note
System Design Guidelines
on http://www.cypress.com.
Logic Block Diagram
256K × 16
RAM Array
I/O0 – I/O7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
I/O8 – I/O15
WE
BLE
BHE
A
1
A
0
A
9
A
10
Power- Down
Circuit
BHE
BLE
CE
CE
A
1
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK256K16SCBU-55BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16SCBU-70BVXI | 功能描述:IC PSRAM 4MBIT 70NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CYK256K16SCBU-70BVXIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 4MBIT 256KX16 70NS 48VFBGA - Tape and Reel |
| CYK256K16SCCB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16SCCBU-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
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