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參數(shù)資料
| 型號： | CYK256K16SCCBU-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Pseudo Static RAM |
| 中文描述： | 256K X 16 PSEUDO STATIC RAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 307K |
| 代理商： | CYK256K16SCCBU-55BVI |
4-Mbit (256K x 16) Pseudo Static RAM
CYK256K16SCCB
Cypress Semiconductor Corporation
Document #: 38-05526 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised October 18, 2006
Features
Advanced low-power MoBL
architecture
High speed: 55 ns, 60 ns and 70 ns
Wide voltage range: 2.7V to 3.3V
Typical active current: 1 mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Functional Description
[1]
The CYK256K16SCCB is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life
(MoBL)
in portable applications such as cellular telephones. The
device can be put into standby mode reducing power
consumption dramatically when deselected (CE
1
LOW, CE
2
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE
1
HIGH, CE
2
LOW, OE is deasserted
HIGH), or during a write operation (Chip Enabled and Write
Enable WE LOW).
Reading from the device is accomplished by asserting the
Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins A
0
through A
17
will appear on
I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. See the Truth Table for a
complete description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
256K x 16
RAM Array
I/O
0
–I/O
7
COLUMN DECODER
S
DATA IN DRIVERS
OE
BLE
I/O
8
–I/O
15
WE
BHE
R
Power
-
Down
Circuit
BHE
BLE
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
1
A
1
A
1
A
1
A
1
A
1
CE
2
CE
1
CE
2
CE
1
Logic Block Diagram
A
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK256K16SCCBU-55BVIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 4MBIT 256KX16 55NS 48VFBGA - Tape and Reel |
| CYK256K16SCCBU-60BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16SCCBU-70BAI | 制造商:Cypress Semiconductor 功能描述: |
| CYK256K16SCCBU-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Pseudo Static RAM |
| CYK512K16SCAU-55BAXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8-Mbit (512K x 16) Pseudo Static RAM |
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