- 您現(xiàn)在的位置：買賣IC網 > PDF目錄379098 > CYDC064B08 (Cypress Semiconductor Corp.) 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM PDF資料下載
參數資料
| 型號： | CYDC064B08 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| 中文描述： | 1.8 4k/8k/16k × 16和8k/16k × 8 ConsuMoBL雙端口靜態(tài)存儲器 |
| 文件頁數： | 5/26頁 |
| 文件大小： | 580K |
| 代理商： | CYDC064B08 |
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E
Page 5 of 26
Functional Description
The
CYDC128B08, CYDC064B08 are low-power CMOS 4k,
8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 16-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 32-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32-bit or wider memory appli-
cations without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
CYDC256B16,
CYDC128B16,
CYDC064B16,
designs,
communications
The
CYDC128B08, CYDC064B08 are available in 100-pin TQFP
packages.
CYDC256B16,
CYDC128B16,
CYDC064B16,
Power Supply
The core voltage (V
CC
) can be 1.8V, 2.5V or 3.0V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the V
DDIOL
and V
DDIOR
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
Table 1
.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user wishes to access a semaphore flag,
Pin Definitions
Left Port
Right Port
Description
CE
L
R/W
L
OE
L
A
0L
–A
13L
I/O
0L
–I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
–A
13R
I/O
0R
–I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
IRR0, IRR1
Chip Enable
Read/Write Enable
Output Enable
Address (A
0
–A
11
for 4k devices; A
0
–A
12
for 8k devices; A
0
–A
13
for 16k devices)
.
Data Bus Input/Output for x16 devices; I/O
0
–I/O
7
for x8 devices.
Semaphore Enable
Upper Byte Select (I/O
8
–I/O
15
for x16 devices; Not applicable for x8 devices)
.
Lower Byte Select (I/O
0
–I/O
7
for x16 devices; Not applicable for x8 devices)
.
Interrupt Flag
Busy Flag
Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.
A13L, A13R for CYDC256B16 and CYDC128B08 devices.
ODR0-ODR4
Output Drive Register; These outputs are Open Drain.
SFEN
Special Function Enable
M/S
Master or Slave Select
V
CC
GND
Core Power
Ground
V
DDIOL
V
DDIOR
NC
Left Port I/O Voltage
Right Port I/O Voltage
No Connect
.
Leave this pin Unconnected.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CYDC064B08-40AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXI | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B16 | Replacement for National Semiconductor part number DM9328N. Buy from authorized manufacturer Rochester Electronics. |
| CYDC064B16-40AXC | 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CYDC064B08-40AXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B08-55AXI | 功能描述:靜態(tài)隨機存取存儲器 64K 8Kx8 Consumer Hi Vol Dual Port IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDC064B16 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
| CYDC064B16-40AXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。