參數(shù)資料
型號: CYD18S72V-133BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
中文描述: 256K X 72 DUAL-PORT SRAM, 5 ns, PBGA484
封裝: 23 X 23 MM, 1 MM, ROHS COMPLIANT, MO-192, FBGA-484
文件頁數(shù): 23/26頁
文件大?。?/td> 470K
代理商: CYD18S72V-133BBC
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 23 of 26
Mailbox Interrupt Timing
[52,53,54,55,56]
Table 7. Read / Write and Enable Operation (Any Port)
[1,14,57,58,59]
Inputs
CE
0
H
Outputs
DQ
0
DQ
71
High-Z
Operation
Deselected
OE
X
CLK
CE
1
X
R/W
X
X
X
L
X
High-Z
Deselected
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Notes:
52. CE
= OE = ADS = CNTEN = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH.
53. Address “1FFFF” is the mailbox location for R_Port.
54. L_Port is configured for Write operation, and R_Port is configured for Read operation.
55. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
56. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
57. OE is an asynchronous input signal.
58. When CE changes state, deselection and Read happen after one cycle of latency.
59. CE
0
= OE = LOW; CE
1
= R/W = HIGH.
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
3FFFF
t
SA
t
HA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
3FFFF
A
m+3
R_PORT
ADDRESS
INT
R
t
SA
t
HA
t
SINT
t
RINT
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