參數(shù)資料
型號: CYD18S72V-133BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
中文描述: 256K X 72 DUAL-PORT SRAM, 5 ns, PBGA484
封裝: 23 X 23 MM, 1 MM, ROHS COMPLIANT, MO-192, FBGA-484
文件頁數(shù): 10/26頁
文件大?。?/td> 470K
代理商: CYD18S72V-133BBC
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 10 of 26
Table 4. Identification Register Definitions
Instruction Field
Revision Number(31:28)
Cypress Device(27:12)
Value
0h
C002h
Description
Reserved for version number
Defines Cypress DIE number for CYD18S72V and
CYD09S72V.
Defines Cypress DIE number for CYD04S72V
Allows unique identification of FLEx72 family device vendor
Indicates the presence of an ID register
C001h
034h
1
Cypress JDEC ID(11:1)
ID Register Presence (0)
Table 5. Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Bit Size
4
1
32
n
[20]
Table 6. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
Code
Description
0000
1111
1011
0111
0100
1000
1100
All other codes
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FLEx72 output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
Other combinations are reserved. Do not use other than the above.
Note:
20. See details in the device BSDL files
TDO
D2
TDI
TDO
D1
TDI
TDO
D4
TDI
TDO
D3
TDI
TDO
TDI
TDO
D2
TDI
TDO
D1
TDI
TDI
TDO
Figure 3. Scan Chain
18 Mbit
4 Mbit/9 Mbit
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