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參數(shù)資料
| 型號： | CYD09S72V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
| 中文描述： | FullFlex器件特別提款權同步雙端口SRAM（FullFlex器件同步雙端口SRAM的特別提款權） |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 774K |
| 代理商： | CYD09S72V18 |
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FullFlex
Document #: 38-06082 Rev. *F
Page 11 of 52
Variable Impedance Matching (VIM)
Each port contains a Variable Impedance Matching circuit to
set the impedance of the I/O driver to match the impedance of
the on-board traces. The impedance is set for all outputs
except JTAG and is done on a per port basis. To take
advantage of the VIM feature, connect a calibrating resistor
(RQ) that is five times the value of the intended line impedance
from the ZQ pin to VSS. The output impedance is then
adjusted to account for drifts in supply voltage and temper-
ature every 1024 clock cycles. If a port’s clock is suspended,
the VIM circuit will retain its last setting until the clock is
restarted. On restart, it will then resume periodic adjustment.
In the case of a significant change in device temperature or
supply voltage, recalibration will happen every 1024 clock
cycles. A Master Reset will initialize the VIM circuitry.
Table 6
shows the VIM parameters and
Table 7
describes the VIM
operation modes.
In order to disable VIM, the ZQ pin must be connected to
VDDIO of the relative supply for the I/Os before a Master
Reset.
Address Counter and Mask Register Operations
[1]
Each port of the FullFlex family contains a programmable burst
address counter. The burst counter contains four registers: a
counter register, a mask register, a mirror register, and a busy
address register.
The
counter register
contains the address used to access the
RAM array. It is changed only by the master reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
The
mask register
value affects the Counter Increment and
Counter Reset operations by preventing the corresponding
bits of the counter register from changing. It also affects the
counter interrupt output (CNTINT). The mask register is only
changed by Mask Reset, Mask Load, and MRST. The Mask
Load operation loads the value of the address bus into the
mask register. The mask register defines the counting range
of the counter register. The mask register is divided into two or
three consecutive regions. Zero or more “0s” define the
masked region and one or more “1s” define the unmasked
portion of the counter register. The counter register may only
be divided into up to three regions. The region containing the
least significant bits must be no more than two “0s”. Bits one
and zero may be “10” respectively, masking the least signif-
icant counter bit and causing the counter to increment by two
instead of one. If bits one and zero are “00”, the two least
significant bits are masked and the counter will increment by
four instead of one. For example, in the case of a 256Kx72
Table 5. Deterministic Access Control Logic
Left Port
Right Port Left Clock
Right Clock
BUSY
L
H
BUSY
R
H
Description
Read
Read
X
X
No Collision
Write
Read
>t
CCS
0
0
H
H
Read OLD Data
>t
CCS
0
H
H
Read NEW Data
<t
CCS
H
H
Read OLD Data
H
L
Data Not Guaranteed
0
<t
CCS
H
H
Read NEW Data
H
L
Data Not Guaranteed
Read
Write
>t
CCS
0
0
H
H
Read NEW Data
>t
CCS
0
H
H
Read OLD Data
<t
CCS
H
H
Read NEW Data
L
H
Data Not Guaranteed
0
<t
CCS
H
H
Read OLD Data
L
H
Data Not Guaranteed
Write
Write
0
>–t
CCS
& <t
CCS
>t
CCS
0
L
L
Array Data Corrupted
0
L
H
Array Stores Right Port Data
>t
CCS
H
L
Array Stores Left Port Data
Table 6. Variable Impedance Matching Parameters
Parameter
Min.
100
20
N/A
N/A
Max.
275
55
1024
1024
Unit
Cycles
Cycles
Tolerance
± 2%
± 15%
N/A
N/A
RQ Value
Output Impedance
Reset Time
Update Time
Table 7. Variable Impedance Matching Operation
RQ Connection
100
- 275
to VSS Output Driver Impedance = RQ/5 ±
15% at Vout = VDDIO/2
ZQ
to VDDIO
VIM Disabled. Rout < 20
at Vout =
VDDIO/2
Output Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYD09S72V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 9216K (128Kx72) 1.8v 167MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD09S72V18-167BBXI | 功能描述:IC SRAM 9MBIT 167MHZ 256LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CYD09S72V18-167BGXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CYD09S72V18-167BGXI | 制造商:Cypress Semiconductor 功能描述: |
| CYD09S72V18-200BBXC | 功能描述:靜態(tài)隨機存取存儲器 FullFlex72 9MSync DP 128Kx72, 90nm, SDR RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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