參數(shù)資料
型號(hào)： CYD09S72V-133BBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
中文描述： 128K X 72 DUAL-PORT SRAM, 4.4 ns, PBGA484
封裝： 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, MO-192, FBGA-484
文件頁數(shù)： 11/26頁
文件大?。?/td> 470K
代理商： CYD09S72V-133BBI
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 11 of 26
Maximum Ratings
[21]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65
°
C to + 150
°
C
Ambient Temperature with
Power Applied............................................–55
°
C to + 125
°
C
Supply Voltage to Ground Potential..............–0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to V
DD
+ 0.5V
DC Input Voltage .............................. –0.5V to V
DD
+ 0.5V
[22]
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
V
DD
3.3V
± 165 mV
V
CORE
1.8V
± 100 mV
Commercial
Industrial
–40
°
C to +85
°
C
3.3V
± 165 mV
1.8V
± 100mV
Electrical Characteristics
Over the Operating Range
Parameter
Description
Part No.
-167
Typ.
-133
Typ.
-100
Typ
Unit
Min.
Max.
Min.
Max.
Min.
Max
V
OH
Output HIGH Voltage (V
DD
= Min., I
OH
= –4.0
mA)
2.4
2.4
2.4
V
V
OL
Output LOW Voltage (V
DD
= Min., I
OL
= +4.0
mA)
0.4
0.4
0.4
V
V
IH
V
IL
I
OZ
I
IX1
Input HIGH Voltage
2.0
2.0
2.0
V
Input LOW Voltage
0.8
0.8
0.8
V
μ
A
μ
A
Output Leakage Current
–10
10
–10
10
-10
10
Input Leakage Current Except TDI, TMS,
MRST
–10
10
–10
10
-10
10
I
IX2
I
CC
Input Leakage Current TDI, TMS, MRST
–0.1
1.0
–0.1
1.0
-0.1
1.0
mA
Operating Current
(V
= Max.,I
= 0 mA),
Outputs Disabled
CYD04S72V
CYD09S72V
225
300
225
300
mA
CYD18S72V
410
580
315
450
mA
I
SB1
Standby Current
(Both Ports TTL Level)
CE
L
and CE
R
≥
V
IH
, f = f
MAX
Standby Current
(One Port TTL Level)
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Standby Current (Both Ports
CMOS Level) CE
L
and CE
R
≥
V
DD
– 0.2V, f = 0
Standby Current
(One Port CMOS Level)
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Operating Current
(VDDIO = Max,Iout=0mA,f=0)
Outputs Disabled
CYD04S72V
CYD09S72V
90
115
90
115
mA
I
SB2
CYD04S72V
CYD09S72V
160
210
160
210
mA
I
SB3
CYD04S72V
CYD09S72V
55
75
55
75
mA
I
SB4
CYD04S72V
CYD09S72V
160
210
160
210
mA
I
SB5
CYD18S72V
75
75
mA
I
CORE
Core Operating Current for (V
DD
= Max.,I
OUT
= 0 mA), Outputs Disabled
0
0
0
0
0
0
mA
Capacitance
[23]
Part#
Parameter
Description
Test Conditions
Max.
Unit
CYD04S72V
CYD09S72V
C
IN
C
OUT
C
IN
C
OUT
Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V
20
pF
Output Capacitance
10
[24]
pF
CYD18S72V
Input Capacitance
40
pF
Output Capacitance
20
pF
Note:
21. The voltage on any input or I/O pin can not exceed the power pin during power-up.
22. Pulse width < 20 ns.
23. C
OUT
also references C
I/O
相關(guān)PDF資料
PDF描述
CYD09S72V-167BBC FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBC FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBI FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-133BBC FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S36V FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM)
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