參數(shù)資料
型號(hào): CYD04S72V
廠商: Cypress Semiconductor Corp.
英文描述: FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
中文描述: FLEx72 3.3 64K/128K/256K × 72同步雙口RAM
文件頁(yè)數(shù): 23/26頁(yè)
文件大?。?/td> 470K
代理商: CYD04S72V
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 23 of 26
Mailbox Interrupt Timing
[52,53,54,55,56]
Table 7. Read / Write and Enable Operation (Any Port)
[1,14,57,58,59]
Inputs
CE
0
H
Outputs
DQ
0
DQ
71
High-Z
Operation
Deselected
OE
X
CLK
CE
1
X
R/W
X
X
X
L
X
High-Z
Deselected
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Notes:
52. CE
= OE = ADS = CNTEN = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH.
53. Address “1FFFF” is the mailbox location for R_Port.
54. L_Port is configured for Write operation, and R_Port is configured for Read operation.
55. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
56. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
57. OE is an asynchronous input signal.
58. When CE changes state, deselection and Read happen after one cycle of latency.
59. CE
0
= OE = LOW; CE
1
= R/W = HIGH.
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
3FFFF
t
SA
t
HA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
3FFFF
A
m+3
R_PORT
ADDRESS
INT
R
t
SA
t
HA
t
SINT
t
RINT
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CYD04S72V-133BBI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64K x 72 3.3V IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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