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參數(shù)資料
| 型號(hào)： | CYD04S72V-167BBC |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| 中文描述： | 64K X 72 DUAL-PORT SRAM, 4 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM, ROHS COMPLIANT, MO-192, FBGA-484 |
| 文件頁(yè)數(shù)： | 4/26頁(yè) |
| 文件大小： | 470K |
| 代理商： | CYD04S72V-167BBC |
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PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 4 of 26
Pin Definitions
Left Port
Right Port
Description
A
0L
–A
17L
A
0R
–A
17R
Address Inputs
.
BE
0L
–BE
7L
BE
0R
–BE
7R
Byte Enable Inputs
. Asserting these signals enables Read and Write opera-
tions to the corresponding bytes of the memory array.
Port Busy Output
.
When the collision is detected, a BUSY is asserted.
BUSY
L[2,5]
BUSY
R[2,5]
C
L
C
R
Input Clock Signal
.
CE0
L[9]
CE0
R[9]
Active Low Chip Enable Input
.
CE1
L[8]
CE1
R[8]
Active High Chip Enable Input
.
DQ
0L
–DQ
71L
DQ
0R
–DQ
71R
Data Bus Input/Output
.
OE
L
OE
R
Output Enable Input
. This asynchronous signal must be asserted LOW to
enable the DQ data pins during Read operations.
Mailbox Interrupt Flag Output
.
The mailbox permits communications
between ports. The upper two memory locations can be used for message
passing. INT
L
is asserted LOW when the right port writes to the mailbox location
of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
Port Low Speed Select Input
.
When operating at less than 100 MHz, the
LowSPD disables the port DLL.
Port Address/Control/Data I/O Standard Select Input
.
INT
L
INT
R
LowSPD
L[2,4]
LowSPD
R[2,4]
PORTSTD[1:0]
L[2,4,5]
PORTSTD[1:0]
R[2,4,5]
R/W
L
R/W
R
Read/Write Enable Input
. Assert this pin LOW to write to, or HIGH to Read
from the dual port memory array.
Port Ready Output
.
This signal will be asserted when a port is ready for normal
operation.
Port Counter/Mask Select Input
.
Counter control input.
READY
L[2,5]
READY
R[2,5]
CNT/MSK
L[8]
CNT/MSK
R[8]
ADS
L[9]
ADS
R[9]
Port Counter Address Load Strobe Input
.
Counter control input.
CNTEN
L[9]
CNTEN
R[9]
Port Counter Enable Input
.
Counter control input.
CNTRST
L[8]
CNTRST
R[8]
Port Counter Reset Input
. Counter control input.
CNTINT
L[10]
CNTINT
R[10]
Port Counter Interrupt Output
. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
Port Counter Wrap Input
.
After the burst counter reaches the maximum count,
if WRP is low, the unmasked counter bits will be set to 0. If high, the counter
will be loaded with the value stored in the mirror register.
Port Counter Retransmit Input
.
Counter control input.
WRP
L[2,3]
WRP
R[2,3]
RET
L[2,3]
RET
R[2,3]
FTSEL
L[2,3]
FTSEL
R[2,3]
Flow-Through Select
. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
Port External High-Speed IO Reference Input
.
VREF
L[2,5]
VREF
R[2,5]
VDDIO
L
VDDIO
R
Port IO Power Supply
.
REV
[2,4]L
REV
[2,4]R
Reserved pins for future features
.
MRST
Master Reset Input
. MRST is an asynchronous input signal and affects both
ports. A master reset operation is required at power-up.
JTAG Reset Input
.
TRST
[2,5]
TMS
JTAG Test Mode Select Input
. It controls the advance of JTAG TAP state
machine. State machine transitions occur on the rising edge of TCK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYD04S72V18-167BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64Kx72 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD04S72V18-167BBXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64Kx72 90nm IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD04S72V18-200BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64Kx72 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD04S72V18-200BBXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64Kx72 90nm IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD04S72V18-250BBXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 64Kx72 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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