參數(shù)資料
型號： CY8C27443-24PVI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO28
封裝： 0.210 INCH, LEAD FREE, SSOP-28
文件頁數(shù)： 34/44頁
文件大?。?/td> 542K
代理商： CY8C27443-24PVI
August 3, 2004
Document No. 38-12012 Rev. *I
34
CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-25. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-26. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency with CPU Clock divide by 1
a
a. MaximumCPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximumfrequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
0.093
–
12.3
MHz
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
b
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-27. AC Programming Specifications
Symbol
T
RSCLK
T
FSCLK
T
SSCLK
T
HSCLK
F
SCLK
T
ERASEB
T
WRITE
T
DSCLK
T
DSCLK3
Description
Min
Typ
Max
Units
ns
Notes
Rise Time of SCLK
1
–
20
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
Frequency of SCLK
0
–
8
MHz
Flash Erase Time (Block)
–
10
–
ms
Flash Block Write Time
–
10
–
ms
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd
>
3.6
3.0
≤
Vdd
≤
3.6
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
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CY8C27443-24PVXIT 功能描述:可編程片上系統(tǒng) - PSoC 16K FlSh 256B RAM IND RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風格:SMD/SMT
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CY8C27443-24PXIES 制造商:Cypress Semiconductor 功能描述:
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