參數(shù)資料
型號(hào)： CY8C27443-24PVI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO28
封裝： 0.210 INCH, LEAD FREE, SSOP-28
文件頁(yè)數(shù)： 19/44頁(yè)
文件大?。?/td> 542K
代理商： CY8C27443-24PVI
August 3, 2004
Document No. 38-12012 Rev. *I
19
CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3
DC Electrical Characteristics
3.3.1
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol
Vdd
I
DD
Description
Min
Typ
Max
Units
Notes
Supply Voltage
Supply Current
3.00
–
–
5
5.25
8
V
mA
Conditions are Vdd = 5.0V, T
A
= 25
o
C, CPU = 3
MHz, 48 MHz = Disabled. VC1 = 1.5 MHz, VC2
= 93.75 kHz, VC3 = 93.75 kHz.
Conditions are Vdd = 3.3V, T
A
= 25
o
C, CPU = 3
MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2
= 93.75 kHz, VC3 = 93.75 kHz.
Conditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, -40
o
C
≤
T
A
≤
55
o
C.
Conditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, 55
o
C < T
A
≤
85
o
C.
Conditions are with properly loaded, 1
μ
W max,
32.768 kHz crystal. Vdd = 3.3V, -40
o
C
≤
T
A
≤
55
o
C.
Conditions are with properly loaded, 1
μ
W max,
32.768 kHz crystal. Vdd = 3.3V, 55
o
C < T
A
≤
85
o
C.
Trimmed for appropriate Vdd.
I
DD3
Supply Current
–
3.3
6.0
mA
I
SB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.
a
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable systemoperation. This should be compared with devices that have simlar functions
enabled.
b. Refer to the
Ordering Informationchapter on page42
.
–
3
6.5
μ
A
I
SBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.
a
–
4
25
μ
A
I
SBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal.
a
–
4
7.5
μ
A
I
SBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.
a
–
5
26
μ
A
V
REF
V
REF
Reference Voltage (Bandgap) for Silicon A
b
Reference Voltage (Bandgap) for Silicon B
b
1.275
1.300
1.325
V
1.280
1.300
1.320
V
Trimmed for appropriate Vdd.
Table 3-5. DC GPIO Specifications
Symbol
R
PU
R
PD
V
OH
Description
Min
Typ
Max
Units
k
k
V
Notes
Pull up Resistor
4
5.6
8
Pull down Resistor
4
5.6
8
High Output Level
Vdd - 1.0
–
–
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
Vdd = 3.0 to 5.25
V
OL
Low Output Level
–
–
0.75
V
V
IL
V
IH
V
H
I
IL
C
IN
C
OUT
Input Low Level
–
–
0.8
V
Input High Level
2.1
–
V
Vdd = 3.0 to 5.25
Input Hysterisis
–
60
–
mV
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1
μ
A.
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25
o
C.
Package and pin dependent. Temp = 25
o
C.
Capacitive Load on Pins as Output
–
3.5
10
pF
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