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參數(shù)資料
| 型號： | CY8C24794-SPC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoCTM Mixed-Signal Array |
| 中文描述： | PSoCTM混合信號陣列 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 366K |
| 代理商： | CY8C24794-SPC |
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April 14, 2005
Document No. 38-12018 Rev. *F
25
CY8C24794 Final Data Sheet
3. Electrical Specifications
3.4.5
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-21. AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
Notes
Timer
Capture Pulse Width
50
a
a. 50 ns mnimuminput pulse width is based on the input synchronizers running at 24 MHz (42 ns nomnal period).
–
–
ns
Maximum Frequency, No Capture
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture
–
–
25.92
MHz
Counter
Enable Pulse Width
50
a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input
–
–
25.92
MHz
Dead Band
Kill Pulse Width:
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50
a
–
–
ns
Disable Mode
50
a
–
–
ns
Maximum Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
50
a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Table 3-22. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency for USB Applications
23.94
24
24.06
MHz
–
Duty Cycle
47
50
53
%
μ
s
–
Power up to IMO Switch
150
–
–
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PDF描述 |
|---|---|
| CY8C24794-SPSX | PSoCTM Mixed-Signal Array |
| CY8C27543-24AXI | PSoC Mixed Signal Array |
| CY8C27643-24LFI | PSoC Mixed Signal Array |
| CY8C27643-24LFIT | PSoC Mixed Signal Array |
| CY8C27643-24LFXI | PSoC Mixed Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C24794-SPE | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoCTM Mixed-Signal Array |
| CY8C24794-SPI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoCTM Mixed-Signal Array |
| CY8C24794-SPLFX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoCTM Mixed-Signal Array |
| CY8C24794-SPPVX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoCTM Mixed-Signal Array |
| CY8C24794-SPPX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoCTM Mixed-Signal Array |
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