參數(shù)資料
型號(hào): CY8C21123
廠商: Cypress Semiconductor Corp.
英文描述: PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
中文描述: PSoC混合信號(hào)陣列(的PSoC混合信號(hào)陣列)
文件頁數(shù): 9/33頁
文件大小: 325K
代理商: CY8C21123
February 25, 2005
Document No. 38-12022 Rev. *G
9
CY8C21x23 Final Data Sheet
1. Pin Information
1.1.3
20-Pin Part Pinout
Table 1-3. 20-Pin Part Pinout (SSOP)
Pin
No.
Type
Name
Description
CY8C21323 20-Pin PSoC Device
Digital
IO
IO
IO
IO
Analog
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
P0[7]
P0[5]
P0[3]
P0[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Ground connection.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Power
IO
IO
IO
IO
I2C Serial Clock (SCL), ISSP-SCLK.
Ground connection.
I2C Serial Data (SDA), ISSP-SDATA.
Power
IO
IO
IO
Optional External Clock Input (EXT-
CLK).
14
15
IO
P1[6]
XRES
Input
Active high external reset with internal
pull down.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
16
17
18
19
20
IO
IO
IO
IO
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Power
LEGEND
A = Analog, I = Input, and O = Output.
SSOP
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], 2C SDA
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, P1[1]
Vss
Vss
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