- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378513 > CY8C21123 (Cypress Semiconductor Corp.) PSoC Mixed-Signal Array(PSoC混合信號陣列) PDF資料下載
參數(shù)資料
| 型號： | CY8C21123 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed-Signal Array(PSoC混合信號陣列) |
| 中文描述： | PSoC混合信號陣列（的PSoC混合信號陣列） |
| 文件頁數(shù)： | 26/33頁 |
| 文件大?。?/td> | 325K |
| 代理商： | CY8C21123 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
February 25, 2005
Document No. 38-12022 Rev. *G
26
CY8C21x23 Final Data Sheet
3. Electrical Specifications
3.4.5
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25
°
C
and are for design guidance only.
Table 3-21. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
–
Frequency
0.093
–
24.6
MHz
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-22. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the external
clock must adhere to the maximum frequency
and duty cycle requirements.
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
24.6
MHz
If the frequency of the external clock is greater
than 12 MHz, the CPU clock divider must be set
to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-23. 2.7V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency with CPU Clock divide by 1
0.093
–
6.06
0
MHz
Maximum CPU frequency is 3 MHz at 2.7V.
With the CPU clock divider set to 1, the external
clock must adhere to the maximum frequency
and duty cycle requirements.
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
12.12
MHz
If the frequency of the external clock is greater
than 3 MHz, the CPU clock divider must be set
to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock divide by 1
83.4
–
5300
ns
–
Low Period with CPU Clock divide by 1
83.4
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C21223 | PSoC Mixed-Signal Array(PSoC混合信號陣列) |
| CY8C21634-24AX | PSoC Mixed-Signal Array |
| CY8C21534 | PSoC Mixed-Signal Array |
| CY8C21234-24LFX | PQ I HIP6W DUET |
| CY8C21434-24LFX | PSoC Mixed-Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C21123_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip |
| CY8C21123_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip Low power at high speed |
| CY8C21123_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC?? Programmable System-on-Chipa?￠ |
| CY8C2112324SXI | 制造商:Cypress Semiconductor 功能描述: |
| CY8C21123-24SXI | 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 4K FLASH 256B SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。