參數(shù)資料
型號: CY8C20334
廠商: Cypress Semiconductor Corp.
英文描述: PSoC Mixed-Signal Array(PSoC混合信號陣列)
中文描述: PSoC混合信號陣列(的PSoC混合信號陣列)
文件頁數(shù): 22/32頁
文件大小: 378K
代理商: CY8C20334
September 18, 2006
Document No. 001-05356 Rev. *B
22
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet
2. Electrical Specifications
2.4.8
AC I
2
C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
T
A
85
°
C, 3.0V to 3.6V and -40
°
C
T
A
85
°
C, or 2.4V to 3.0V and -40
°
C
T
A
85
°
C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25
°
C and are for design guidance only.
Figure 2-3. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 2-22. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd
3.0V
Symbol
F
SCLI2C
T
HDSTAI2C
Description
Standard Mode
Min
Fast Mode
Min
Units
kHz
μ
s
Notes
Max
Max
SCL Clock Frequency
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition 4.7
Pulse Width of spikes are suppressed by the input fil-
ter.
0
4.0
100
0
0.6
400
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
4.7
4.0
4.7
0
250
4.0
1.3
0.6
0.6
0
100
a
0.6
1.3
0
50
μ
s
μ
s
μ
s
μ
s
ns
μ
s
μ
s
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system but the requirement t
250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Table 2-23. 2.7V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode not Supported)
Symbol
F
SCLI2C
T
HDSTAI2C
Description
Standard Mode
Min
Fast Mode
Min
Units
kHz
μ
s
Notes
Max
Max
SCL Clock Frequency
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition 4.7
Pulse Width of spikes are suppressed by the input fil-
ter.
0
4.0
100
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
4.7
4.0
4.7
0
250
4.0
μ
s
μ
s
μ
s
μ
s
ns
μ
s
μ
s
ns
SDA
SCL
S
Sr
S
P
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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CY8C20334-12LKXIT 功能描述:可編程片上系統(tǒng) - PSoC 20 I/O 8K Flash 512B RAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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