參數(shù)資料
型號(hào)： CY7C68014A
廠商： Cypress Semiconductor Corp.
英文描述： EZ-USB FX2LP USB Microcontroller
中文描述： 的EZ - USB FX2LP的USB微控制器
文件頁數(shù)： 28/55頁
文件大小： 1958K
代理商： CY7C68014A
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 28 of 55
5.0
Register Summary
FX2LP register bit definitions are described in the FX2LP TRM
in greater detail.
Table 5-1. FX2LP Register Summary
Hex
Size Name
GPIF Waveform Memories
E400 128 WAVEDATA
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
GPIF Waveform
Descriptor 0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
E480 128 reserved
GENERAL CONFIGURATION
CPUCS
IFCONFIG
E600 1
E601 1
CPU Control & Status
Interface Configuration
(Ports, GPIF, slave FIFOs)
Slave FIFO FLAGA and
FLAGB Pin Configuration
Slave FIFO FLAGC and
FLAGD Pin Configuration
Restore FIFOS to default
state
Breakpoint Control
Breakpoint Address H
Breakpoint Address L
230 Kbaud internally
generated ref. clock
Slave FIFO Interface pins
polarity
Chip Revision
0
IFCLKSRC
0
3048MHZ
PORTCSTB CLKSPD1
IFCLKOE
CLKSPD0
ASYNC
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
IFCLKPOL
E602 1
PINFLAGSAB
[11]
PINFLAGSCD
[11]
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000 RW
E603 1
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000 RW
E604 1
FIFORESET
[11]
BREAKPT
BPADDRH
BPADDRL
UART230
NAKALL
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
E605 1
E606 1
E607 1
E608 1
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
0
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
A8
A0
230UART0
00000000 rrrrbbbr
xxxxxxxx
xxxxxxxx
00000000 rrrrrrbb
RW
RW
E609 1
FIFOPINPOLAR
[11]
REVID
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
E60A 1
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
RevA
00000001
00000000 rrrrrrbb
R
E60B 1
REVCTL
[11]
UDMA
GPIFHOLDAMOUNT MSTB Hold Time
Chip Revision Control
0
0
0
0
0
0
dyn_out
enh_pkt
E60C 1
(for UDMA)
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
E610 1
Endpoint 1-OUT
Configuration
Endpoint 1-IN
Configuration
Endpoint 2 Configuration VALID
Endpoint 4 Configuration VALID
Endpoint 6 Configuration VALID
Endpoint 8 Configuration VALID
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E611 1
EP1INCFG
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E612 1
E613 1
E614 1
E615 1
EP2CFG
EP4CFG
EP6CFG
EP8CFG
reserved
EP2FIFOCFG
[11]
EP4FIFOCFG
[11]
EP6FIFOCFG
[11]
EP8FIFOCFG
[11]
reserved
EP2AUTOINLENH
[11
Endpoint 2 AUTOIN
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
SIZE
0
0
0
0
0
BUF1
0
BUF1
0
BUF0
0
BUF0
0
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
2
E618 1
Endpoint 2 / slave FIFO
configuration
Endpoint 4 / slave FIFO
configuration
Endpoint 6 / slave FIFO
configuration
Endpoint 8 / slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
E619 1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
E61A 1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
E61B 1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
E61C 4
E620 1
Packet Length H
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E621 1
EP2AUTOINLENL
[11]
Endpoint 2 AUTOIN
Packet Length L
Endpoint 4 AUTOIN
Packet Length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E622 1
EP4AUTOINLENH
[11
]
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E623 1
EP4AUTOINLENL
[11]
Endpoint 4 AUTOIN
Packet Length L
Endpoint 6 AUTOIN
Packet Length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E624 1
EP6AUTOINLENH
[11
]
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E625 1
EP6AUTOINLENL
[11]
Endpoint 6 AUTOIN
Packet Length L
Endpoint 8 AUTOIN
Packet Length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E626 1
EP8AUTOINLENH
[11
]
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E627 1
EP8AUTOINLENL
[11]
Endpoint 8 AUTOIN
Packet Length L
ECC Configuration
ECC Reset
ECC1 Byte 0 Address
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E628 1
E629 1
E62A 1
E62B 1
E62C 1
E62D 1
Note:
11.
ECCCFG
ECCRESET
ECC1B0
ECC1B1
ECC1B2
ECC2B0
0
x
LINE15
LINE7
COL5
LINE15
0
x
LINE14
LINE6
COL4
LINE14
0
x
LINE13
LINE5
COL3
LINE13
0
x
LINE12
LINE4
COL2
LINE12
0
x
LINE11
LINE3
COL1
LINE11
0
x
LINE10
LINE2
COL0
LINE10
0
x
LINE9
LINE1
LINE17
LINE9
ECCM
x
LINE8
LINE0
LINE16
LINE8
00000000 rrrrrrrb
00000000 W
00000000 R
00000000 R
00000000 R
00000000 R
Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C68014A-100AXC 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery App High COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C68014A-100AXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C68014A-128AXC 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery App High COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C68014A-56BAXC 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery PWR LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C68014A-56LFXC 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery Apps LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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