參數(shù)資料
型號: CY7C64113
廠商: Cypress Semiconductor Corp.
英文描述: Full-Speed USB (12 Mbps) Function(全速 USB (12 Mbps)性能)
中文描述: 全速USB(12 Mbps)的功能(全速的USB(12 Mbps)的性能)
文件頁數(shù): 27/46頁
文件大?。?/td> 381K
代理商: CY7C64113
CY7C64013
CY7C64113
PRELIMINARY
27
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
The Interrupt Vectors supported by the USB Controller are listed in
Table 16-1
. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I
2
C interrupt) has the lowest priority. Although Reset is not
an interrupt, the first instruction executed after a reset is at PROM address 0x0000h
which corresponds to the first entry in the
Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
Interrupt Vectors
Figure 16-3. Interrupt Controller Functional Diagram
CLR
Global
Interrupt
Enable
Bit
Interrupt
Acknowledge
IRQout
USB Reset Clear
Interrupt
Vector
Interrupt
Priority
Encoder
Enable [0]
(Reg 0x20)
D
Q
1
CLR
USB Reset IRQ
128-
μ
s CLR
128-
μ
s IRQ
1-ms CLR
1-ms IRQ
AddA EP0 CLR
AddA EP0 IRQ
AddA EP1 CLR
I
2
C IRQ
Enable [6]
(Reg 0x20)
CLK
CLR
D
Q
CLK
1
I
2
C CLR
Int
I
2
C
Int
USB
Reset
AddA EP1 IRQ
AddA EP2 CLR
IRQ Sense
IRQ
Controlled by DI, EI, and
RETI Instructions
DAC IRQ
GPIO CLR
DAC CLR
To CPU
CPU
GPIO IRQ
AddA EP2 IRQ
AddA EP3 CLR
AddA EP3 IRQ
AddA EP4 CLR
AddA EP4 IRQ
CLR
Enable [2]
(Reg 0x21)
D
Q
1
CLK
Int
AddA
ENP2
Int Enable
Sense
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PDF描述
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