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參數(shù)資料
| 型號： | CY7C64113 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Full-Speed USB (12 Mbps) Function(全速 USB (12 Mbps)性能) |
| 中文描述： | 全速USB（12 Mbps）的功能（全速的USB（12 Mbps）的性能） |
| 文件頁數(shù)： | 24/46頁 |
| 文件大小： | 381K |
| 代理商： | CY7C64113 |
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CY7C64013
CY7C64113
PRELIMINARY
24
In master mode, the I
2
C block generates the clock (SCK), and drives the data line as required depending on transmit or receive
state. The I
2
C block performs any required arbitration and clock synchronization. The loss of arbitration results in the clearing of
this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the chip is the target of an
external master that wins arbitration, then the interrupt is held off until the transaction from the external master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I
2
C Stop bit is generated.
Continue / Busy:
This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin.
In other words, the bit has responded to an interrupt request and has completed the required update or read of the data register.
During a read this bit indicates if the hardware is busy and is locking out additional writes to the I
2
C Status and Control register.
This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I
2
C
interrupt, the I
2
C block does not return to the Busy state until firmware sets the Continue bit. This allows the firmware to make
one control register write without the need to check the Busy bit.
Xmit Mode:
This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clear this
bit for receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I
2
C address packet.
The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases always cause transmit
mode for the first byte.
ACK:
This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I
2
C bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I
2
C bus at the ACK bit time. During transmits (Xmit
Mode=1), this bit should be cleared.
Addr:
This bit is set by the I
2
C block during the first byte of a slave receive transaction, after an I
2
C start or restart. The Addr bit
is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has lost arbitration,
and in slave mode it allows the firmware to recognize that a start or restart has occurred.
ARB Lost/Restart:
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along
with the Continue and MSTR Mode bits) to perform an I
2
C restart sequence. The I
2
C target address for the restart must be written
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during
the restart sequence.
Receive Stop:
This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set
if the firmware terminates the I
2
C transaction by not acknowledging the previous byte transmitted on the I
2
C bus, e.g., in receive
mode if firmware sets the Continue bit and clears the ACK bit.
I
2
C Enable:
Set this bit to override GPIO definition with I
2
C function on the two I
2
C pins. When this bit is cleared, these pins are
free to function as GPIOs. In I
2
C mode, the two pins operate in open drain mode, independent of the GPIO configuration setting.
14.0
Hardware Assisted Parallel Interface (HAPI)
The CY7C64x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate
data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I
2
C
Configuration Register (
Figure 12-1
), bits 1 and 0.
Signals are provided on Port 2 to control the HAPI interface.
Table 14-1
describes these signals and the HAPI control bits in the
HAPI/I
2
C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (0x08) to be
overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3
OFF in
Figure 9-1
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C64713 | EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器，全速USB外設(shè)控制器) |
| CY7C64714 | EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器，全速USB外設(shè)控制器) |
| CY7C68001 | EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller |
| CY7C68013 | Universal Serial Bus Microcontroller(EZ-USB FX2 USB 高速USB外圍微控制器) |
| CY7C68015A | EZ-USB FX2LP USB Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C64113A-PVXC | 功能描述:IC MCU 8K FULL SPEED USB 48-SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64113C-PVXC | 功能描述:IC MCU 8K FULL SPEED USB 48-SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64113-PVC | 功能描述:IC MCU 8K FULL SPEED USB 48-SSOP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64113-PVCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C6421528PVXC | 制造商:Cypress Semiconductor 功能描述: |
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