參數(shù)資料
型號： CY7C63823
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁數(shù)： 27/74頁
文件大?。?/td> 1441K
代理商： CY7C63823
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 27 of 74
Figure 12-1. Sleep Timing
12.2
Once asleep, the only event that can wake the system up is
an interrupt. The global interrupt enable of the CPU flag
register does not need to be set. Any unmasked interrupt will
wake the system up. It is optional for the CPU to actually take
the interrupt after the wake up sequence. The wake up
sequence is synchronized to the 32 kHz clock for purposes of
sequencing a startup delay, to allow the Flash memory module
enough time to power up before the CPU asserts the first read
access. Another reason for the delay is to allow the oscillator,
Bandgap, and LVD/POR circuits time to settle before actually
being used in the system. As shown in
Figure 12-2
, the wake
up sequence is as follows:
1.The wake up interrupt occurs and is synchronized by the
negative edge of the 32 kHz clock.
Wake up Sequence
2.At the following positive edge of the 32 kHz clock, the system
wide PD signal is negated. The Flash memory module, internal
oscillator, EFTB, and bandgap circuit are all powered up to a
normal operating state.
3.At the following positive edge of the 32 kHz clock, the current
values for the precision POR and LVD have settled and are
sampled.
4.At the following negative edge of the 32 kHz clock (after
about 15 μS nominal), the BRQ signal is negated by the sleep
logic circuit. On the following CPUCLK, BRA is negated by the
CPU and instruction execution resumes. Note that in
Figure 12-2
fixed function blocks, such as Flash, internal oscil-
lator, EFTB, and bandgap, have about 15 μSec start up. The
wake-up times (interrupt to CPU operational) will range from
75 μS to 105 μS.
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
IOW
SLEEP
BRQ
PD
BRA
CPUCLK
CPU captures
BRQ on next
CPUCLK edge
CPU
responds
with a BRA
On the falling edge of
CPUCLK, PD is asserted.
The 24/48 MHz system clock
is halted; the Flash and
bandgap are powered down
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C63823-3XWC 制造商:Cypress Semiconductor 功能描述:USB - Bulk 制造商:Cypress Semiconductor 功能描述:Bulk / USB Low-Speed Peripherals
CY7C638234-SXC 功能描述:IC USB CONTROLLERS RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
CY7C638235-SXC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C63823-PXC 功能描述:IC USB PERIPHERAL CTRLR 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:CY7C 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
CY7C63823-QXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 24-QSOP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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