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參數(shù)資料
| 型號： | CY7C63310 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
| 中文描述： | enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器） |
| 文件頁數(shù)： | 20/74頁 |
| 文件大?。?/td> | 1441K |
| 代理商： | CY7C63310 |
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CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 20 of 74
Table 10-2. LPOSC Trim (LPOSCTR) [0x36] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
32-KHz Low
Power
Reserved
32-KHz Bias Trim [1:0]
32-KHz Freq Trim [3:0]
Read/Write
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
D
D
D
D
D
D
D
This register is used to calibrate the 32 KHz Low-speed Oscillator. The reset value is undefined but during boot the SROM writes
a calibration value that is determined during manufacturing test. This value should not require change during normal use. This
is the meaning of ‘D’ in the Default field. If the 32 KHz Low-power bit needs to be written, care must be taken not to disturb the
32 KHz Bias Trim and the 32 KHz Freq Trim fields from their factory calibrated values
Bit 7:
32 KHz Low Power
0 = The 32 KHz Low-speed Oscillator operates in normal mode
1 = The 32 KHz Low-speed Oscillator operates in a low-power mode. The oscillator continues to function normally but with
reduced accuracy
Bit 6:
Reserved
Bit [5:4]:
32 KHz Bias Trim [1:0]
These bits control the bias current of the low-power oscillator.
0 0 = Mid bias
0 1 = High bias
1 0 = Reserved
1 1 = Reserved
Important Note:
Do not program the 32 KHz Bias Trim [1:0] field with the reserved 10b value as the oscillator does not oscillate
at all corner conditions with this setting
Bit [3:0]:
32 KHz Freq Trim [3:0]
These bits are used to trim the frequency of the low-power oscillator
Table 10-3. CPU/USB Clock Config
(
CPUCLKCR) [0x30] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
USB CLK/2
Disable
USB CLK Select
Reserved
CPUCLK Select
Read/Write
–
R/W
R/W
–
–
–
–
R/W
Default
0
0
0
0
0
0
0
0
Bit 7:
Reserved
Bit 6:
USB CLK/2 Disable
This bit only affects the USBCLK when the source is the external crystal oscillator. When the USBCLK source is the Internal 24
MHz Oscillator, the divide by two is always enabled
0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24 MHz Oscillator is used, or when
the external source is used with a 24 MHz clock
1 = USBCLK is undivided. Use this setting only with a 12 MHz external clock
Bit 5:
USB CLK Select
This bit controls the clock source for the USB SIE
0 = Internal 24 MHz Oscillator. With the presence of USB traffic, the Internal 24 MHz Oscillator can be trimmed to meet the USB
requirement of 1.5% tolerance (see
Table 10-5
)
1 = External clock—Internal Oscillator is not trimmed to USB traffic.
Proper USB SIE operation requires a 12 MHz or 24 MHz
clock accurate to <1.5%.
Bit [4:1]:
Reserved
Bit 0:
CPU CLK Select
0 = Internal 24 MHz Oscillator.
1 = External clock—External clock at CLKIN (P0.0) pin.
Note:
the CPU speed selection is configured using the OSC_CR0 Register (
Table 10-4
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63310-PXC | 功能描述:USB 接口集成電路 USB 3K Flash 128 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63310-SXC | 功能描述:USB 接口集成電路 USB Peripheral Cntrl 3K/128 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C63310-SXCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C634121C-PVXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C634121C-PXC | 制造商:Cypress Semiconductor 功能描述: |
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