- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378513 > CY7C4851 (Cypress Semiconductor Corp.) 8K x9 x2 Double Sync FIFOs(8K x9 x2 雙路同步先進先出) PDF資料下載
參數(shù)資料
| 型號： | CY7C4851 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K x9 x2 Double Sync FIFOs(8K x9 x2 雙路同步先進先出) |
| 中文描述： | 8K的X9熱賣x2雙同步FIFO的（8K的X9熱賣x2雙路同步先進先出） |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 348K |
| 代理商： | CY7C4851 |
CY7C4801/4811/4821
CY7C4831/4841/4851
8
Notes:
12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.
13. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.
14. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the
pin act as a load enable for the programmable flag offset registers.
Switching Waveforms
(continued)
Reset Timing
t
RS
t
RSR
QA
0
QA
8
(QB
0
QB
8
)
RSA(RSB)
t
RSF
t
RSF
t
RSF
OEA(OEB)=1
OEA(OEB)=0
RENA1, RENA2
(RENB1,RENB2)
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFB, PAFB)
48X1–8
t
RSS
t
RSR
t
RSS
t
RSR
t
RSS
WENA2/LDA
(WENB2/LDB)
WENA1
(WENB1)
[12]
[13]
[14]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4841 | 4K x9 x2 Double Sync FIFOs(4K x9 x2 雙路同步先進先出) |
| CY7C60113 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60123 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60223 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60333 | enCoRe III Low Voltage(enCoRe III低電壓) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4851-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 8K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:8K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C510 | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C510-55GMB | 制造商: 功能描述: 制造商:undefined 功能描述: |
| CY7C51055LMB | 制造商:CYPRESS 功能描述:IC |
| CY7C510-55LMB | 制造商:CYPRESS 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。