- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378513 > CY7C4851 (Cypress Semiconductor Corp.) 8K x9 x2 Double Sync FIFOs(8K x9 x2 雙路同步先進先出) PDF資料下載
參數(shù)資料
| 型號： | CY7C4851 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K x9 x2 Double Sync FIFOs(8K x9 x2 雙路同步先進先出) |
| 中文描述： | 8K的X9熱賣x2雙同步FIFO的（8K的X9熱賣x2雙路同步先進先出） |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 348K |
| 代理商： | CY7C4851 |
CY7C4801/4811/4821
CY7C4831/4841/4851
12
Notes:
17. t
is the minimum time between a rising (WCLKA,WCLKB) and a rising (RCLKA,RCLKB) edge for (PAEA,PAEB ) to change state during that clock cycle. If the time
between the edge of (WCLKA,WCLKB) and the rising (RCLKA,RCLKB) is less than t
SKEW2
, then (PAEA,PAEB ) may not change state until the next RCLK.
18. (PAEA,PAEB) offset = n.
19. If a read is preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when (PAEA,PAEB ) goes LOW.
20. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW.
21. (PAFA,PAFB) offset = m.
22. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841,
8192-m words for CY7C4851.
23. t
is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge for (PAFA,PAFB) to change during that clock cycle. If the time
between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than t
SKEW2
, then (PAFA,PAFB) may not change state until the next
(WCLKA,WCLKB).
Switching Waveforms
(continued)
t
ENH
ProgrammableAlmost Empty Flag Timing
t
CLKH
t
ENS
t
CLKL
t
PAE
N +1 WORDS
IN FIFO
48X1–12
t
ENH
t
ENS
t
ENH
t
ENS
t
PAE
t
SKEW2
[17]
WCLKA,WCLKB
PAEA(PAEB)
RCLKA(RCLKB)
RENA1, RENA2
(RENB1,RENB2)
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
Note
18
Note
19
t
ENH
Programmable Almost Full FlagTiming
t
CLKH
t
ENS
FULL
M WORDS
IN FIFO
t
CLKL
t
ENS
FULL
M+1 WORDS
IN FIFO
48X1–13
t
ENH
t
ENS
t
ENH
t
ENS
t
PAF
t
SKEW2
t
PAF
[22]
[23]
WCLKA,WCLKB
PAFA(PAFB)
RCLKA(RCLKB)
RENA1, RENA2
(RENB1,RENB2)
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
Note
20
Note
21
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4841 | 4K x9 x2 Double Sync FIFOs(4K x9 x2 雙路同步先進先出) |
| CY7C60113 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60123 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60223 | Wireless enCoRe II Microcontroller(無線enCoRe II微控制器) |
| CY7C60333 | enCoRe III Low Voltage(enCoRe III低電壓) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4851-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 8K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:8K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C510 | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C510-55GMB | 制造商: 功能描述: 制造商:undefined 功能描述: |
| CY7C51055LMB | 制造商:CYPRESS 功能描述:IC |
| CY7C510-55LMB | 制造商:CYPRESS 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。