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參數資料
| 型號： | CY7C460A-15PC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| 中文描述： | 8K X 9 OTHER FIFO, 15 ns, PDIP28 |
| 封裝： | 0.600 INCH, DIP-28 |
| 文件頁數： | 8/15頁 |
| 文件大?。?/td> | 250K |
| 代理商： | CY7C460A-15PC |
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Document #: 38-06011 Rev. *A
Page 8 of 15
Architecture
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF), and Full flags (FF) being HIGH. Read (R) and Write
(W) must be HIGH t
RPW
/t
WPW
before and t
RMR
after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
0
D
8
) t
SD
before and t
HD
after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
WEF
after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW t
WHF
after the falling edge of W following the FIFO actu-
ally being half full. Therefore, the HF is active once the FIFO
is filled to half its capacity plus one word. HF will remain LOW
while less than one half of total memory is available for writing.
The LOW-to-HIGH transition of HF occurs t
RHF
after the rising
edge of R when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF
goes LOW t
WFF
after the falling edge of W, during the cycle in
which the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and
the write pointer is not incremented. FF goes HIGH t
RFF
after
a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q
0
Q
8
) are in a high-impedance condition be-
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty
FIFO are ignored and do not increment the read pointer. From
the empty condition, the FIFO can be read t
WEF
after a valid
write.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
(RT) input is active in the standalone and width expansion
modes. The retransmit feature is intended for use when a
Note:
13. Expansion out of device 1 (XO
1
) is connected to expansion in of device 2 (XI
2
).
Switching Waveforms
[7]
(continued)
Expansion TimingDiagrams
C460A
–
15
R
W
XO
1
(XI
2
)
D
0
D
8
DATA VALID
DATA
VALID
DATA
VALID
t
XOL
t
HD
t
SD
t
SD
t
HD
t
XOL
t
LZR
t
A
t
DVR
t
A
t
DVR
t
HZR
XO
1
(XI
2
)
Q
0
Q
8
C460A
–
16
t
WR
t
RR
DATA VALID
t
XOH
t
XOH
[13]
[13]
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|---|---|
| CY7C460A-15PTC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-25JC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-25PC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
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相關代理商/技術參數 |
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|---|---|
| CY7C460A-25JC | 制造商:Cypress Semiconductor 功能描述: |
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