參數資料
型號: CY7C460A-15PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
中文描述: 8K X 9 OTHER FIFO, 15 ns, PDIP28
封裝: 0.600 INCH, DIP-28
文件頁數: 1/15頁
文件大?。?/td> 250K
代理商: CY7C460A-15PC
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
Functional Description
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Cypress Semiconductor Corporation
Document #: 38-06011 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
60A
Features
High-speed, low-power, first-in first-out (FIFO)
memories
8K x 9 FIFO (CY7C460A)
16K x 9 FIFO (CY7C462A)
32K x 9 FIFO (CY7C464A)
64K x 9 FIFO (CY7C466A)
10-ns access times, 20-ns read/write cycle times
High-speed 50-MHz read/write independent of
depth/width
Low operating power
—I
CC
= 60 mA
—I
SB
=8 mA
Asynchronous read/write
Empty and Full flags
Half Full flag (in standalone mode)
Retransmit (in standalone mode)
TTL-compatible
Width and Depth Expansion Capability
5V
±
10% supply
PLCC, LCC, 300-mil and 600-mil DIP packaging
Three-state outputs
Pin compatible density upgrade to CY7C42X/46X family
Pin compatible and functionally equivalent to IDT7205,
IDT7206, IDT7207, IDT7208
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provided to prevent over-
run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The write operation occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the stan-
dalone (single device) and width expansion configurations. In
the depth expansion configuration, this pin provides the ex-
pansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion configurations, a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the data. Read Enable (R) and Write Enable (W) must both be
HIGH during a retransmit cycle, and then R is used to access
the data.
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
fabricated using Cypress
s advanced 0.5μ RAM3 CMOS tech-
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
64K x 9
LogicBlockDiagram
Pin Configurations
PLCC/LCC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
V
CC
D
4
D
5
D
6
D
7
FL/RT
MR
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
4
3
2
1
32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q
7
Q
6
D
6
D
7
NC
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
32K x
9
DATAINPUTS
(D
0
D
8
)
THREE
STATE
BUFFERS
DATAOUTPUTS
(Q
0
-Q
8
)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
D
3
D
8
W
N
V
D
4
D
5
c
Q
3
Q
8
G
N
R
Q
4
Q
5
C46XA
1
C46XA
2
C46XA
3
7C460A
7C462A
7C464A
7C466A
7C460A
7C462A
7C464A
7C466A
RA8K x 9
相關PDF資料
PDF描述
CY7C460A-15PTC Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A-25JC Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A-25PC Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A-25PTC Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C462A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
相關代理商/技術參數
參數描述
CY7C460A-25JC 制造商:Cypress Semiconductor 功能描述:
CY7C460A-25JCT 制造商:Cypress Semiconductor 功能描述:
CY7C460A-25PC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C460A-25PTC 制造商:Cypress Semiconductor 功能描述:
CY7C462A-10JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 16K x 9 32-Pin PLCC 制造商:e2v technologies 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 16K x 9 32-Pin PLCC