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參數(shù)資料
| 型號： | CY7C4425V-25ASC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | OSC 5V SMT 7X5 CMOS PROGRM |
| 中文描述： | 64 X 18 OTHER FIFO, 15 ns, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 409K |
| 代理商： | CY7C4425V-25ASC |
CY7C4425/4205/4215
CY7C4225/4235/4245
8
Notes:
17. When t
> minimum specification, t
(maximum) = t
+ t
. When t
SKEW2
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW2
or t
CLK
+ t
SKEW2
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms
(continued)
D
0
(FIRSTVALIDWRITE)
First Data Word Latency after Reset with Simultaneous Read and Write
t
SKEW2
WEN
WCLK
Q
0
–Q
17
EF
REN
OE
t
OE
t
ENS
t
OLZ
t
DS
RCLK
t
REF
t
A
t
FRL
D
1
D
2
D
3
D
4
D
0
D
1
D
0
–D
17
42X5–9
t
A
[18]
[17]
D1
D0
t
ENS
t
SKEW2
Empty Flag Timing
WEN
WCLK
Q
0
–Q
17
EF
REN
OE
t
DS
t
ENH
RCLK
t
REF
t
A
t
FRL
D
0
–D
17
D0
t
SKEW2
t
FRL
t
REF
t
DS
t
ENS
t
ENH
42X5–10
t
REF
[17]
[17]
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C4225V-25ASC | OSC 5V SMT 7X5 CMOS PROGRM |
| CY7C4425V-35ASC | OSC 5V SMT 7X5 CMOS PROGRM |
| CY7C4225V-35ASC | OSC 5V SMT 7X5 CMOS PROGRM |
| CY7C4235V-15ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4235V-25ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C443-12JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC |
| CY7C443-14DC | 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 28 Pin, Ceramic, DIP |
| CY7C443-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC |
| CY7C443-14JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC T/R |
| CY7C443-30JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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