參數(shù)資料
型號(hào)： CY7C4425V-25ASC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： OSC 5V SMT 7X5 CMOS PROGRM
中文描述： 64 X 18 OTHER FIFO, 15 ns, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
文件頁(yè)數(shù)： 16/25頁(yè)
文件大?。?/td> 409K
代理商： CY7C4425V-25ASC
CY7C4425/4205/4215
CY7C4225/4235/4245
16
Depth Expansion Configuration
(with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requir-
ing more than 64/256/512/1024/2048/4096 words of buffering.
Figure2 shows Depth Expansion using three CY7C42X5s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration.
42X5–23
WRITECLOCK(WCLK)
WRITE ENABLE(WEN)
RESET(RS)
LOAD(LD)
FF
PAF
PAF
FF
EF
PAE
PAE
EF
WXI RXI
FIRSTLOAD(FL)
READCLOCK(RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
PAF
FF
EF
PAE
WXI RXI
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
V
CC
FIRSTLOAD(FL)
PAF
FF
EF
PAE
WXI RXI
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
V
CC
FIRSTLOAD(FL)
DATAIN (D)
DATAOUT(Q)
相關(guān)PDF資料
PDF描述
CY7C4225V-25ASC OSC 5V SMT 7X5 CMOS PROGRM
CY7C4425V-35ASC OSC 5V SMT 7X5 CMOS PROGRM
CY7C4225V-35ASC OSC 5V SMT 7X5 CMOS PROGRM
CY7C4235V-15ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4235V-25ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C443-12JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC
CY7C443-14DC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 28 Pin, Ceramic, DIP
CY7C443-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC
CY7C443-14JCT 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC T/R
CY7C443-30JC 制造商:Rochester Electronics LLC 功能描述:- Bulk
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