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參數(shù)資料
| 型號(hào)： | CY7C441 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clocked 512 x 9 FIFOs(512 x 9定時(shí)的先進(jìn)先出) |
| 中文描述： | 時(shí)鐘512 × 9先進(jìn)先出（512 × 9定時(shí)的先進(jìn)先出） |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 237K |
| 代理商： | CY7C441 |
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Clocked 512 x 9, 2K x 9 FIFOs
CY7C441
CY7C443
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1989 - Revised January 2, 1997
Features
High-speed, low-power, first-in first-out (FIFO)
memories
512 x 9 (CY7C441)
2,048 x 9 (CY7C443)
0.65 micron CMOS for optimum speed/power
High-speed 83-MHz operation (12 ns read/write cycle
time)
Low power — I
CC
=70 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Almost Empty, and Almost Full status flags
TTL compatible
Parity generation/checking
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Center power and ground pins for reduced noise
Width Expansion Capability
Available in PLCC packages
Functional Description
The CY7C441 and CY7C443 are high-speed, low-power,
first-in first-out (FIFO) memories with clocked read and write
interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a
512 word by 9 bit memory array, while the CY7C443 has a
2048 word by 9 bit memory array. These devices provide so-
lutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the
FIFO on the rising edge of the CKW signal. While ENW is held
active, data is continually written into the FIFO on each CKW
cycle. The output port is controlled in a similar manner by a
free-running read clock (CKR) and a read enable pin (ENR).
The read (CKR) and write (CKW) clocks may be tied together
for single-clock operation or the two clocks may be run inde-
pendently for asynchronous read/write applications. Clock fre-
quencies up to 83.3 MHz are acceptable.
The CY7C441 and CY7C443 clocked FIFOs provide two sta-
tus flag pins (F1 and F2). These flags are decoded to deter-
mine one of four states: Empty, Almost Empty, Intermediate,
and Almost Full (Table 1). The flags are synchronous; i.e.,
change state relative to either the read clock (CKR) or the write
clock (CKW). The Empty and Almost Empty states are updat-
ed exclusively by the CKR while Almost Full is updated exclu-
sively by CKW. The synchronous flag architecture guarantees
that the flags maintain their status for some minimum time.
The CY7C441 and the CY7C443 use center power and ground
for reduced noise. Both configurations are fabricated using an
advanced .65
μ
m CMOS technology. Input ESD protection is
greater than 2001V, and latch-up is prevented by reliable lay-
out techniques and guard rings.
Logic Block Diagram
Pin Configuration
C441-1
C441-2
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14 15 16 17
26
25
24
23
22
21
Top View
PLCC
1819 20
27
28
29
32
7C443
7C441
D
7
D
8
NC
MR
V
SS
CKR
ENR
Q
8
Q
7
D
0
ENW
CKW
V
CC
V
SS
F1
F2
NC
Q
0
D
0–8
CKW
ENW
MR
Q
0–8
ENR
CKR
F
1
F
2
INPUT
REGISTER
RAM
ARRAY
512x 9
2048x 9
OUTPUT
REGISTER
READ
CONTROL
LOGIC
FLAG
LOGIC
WRITE
CONTROL
LOGIC
RESET
LOGIC
READ
POINTER
WRITE
POINTER
D
1
D
2
D
3
NCD
4
D
5
D
6
Q
1
Q
2
NC
Q
3
Q
4
Q
5
Q
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C443 | Clocked 2K x 9 FIFOs(2Kx 9定時(shí)的先進(jìn)先出) |
| CY7C456 | 1K x 18 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的1Kx18可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C455 | 512 x 18 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x18可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C457 | 2K x 18 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx18可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C4831 | 2K x9 x2 Double Sync FIFOs(2K x9 x2 雙路同步先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C441-30JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4421-10JXC | 功能描述:IC SYNC FIFO 64KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4421-10JXCT | 功能描述:IC SYNC FIFO 64KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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