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參數(shù)資料
| 型號： | CY7C457 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2K x 18 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx18可級聯(lián)定時的先進先出) |
| 中文描述： | 2K × 18級聯(lián)與時鐘FIFO的可編程標志（帶可編程標記的2Kx18可級聯(lián)定時的先進先出） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 437K |
| 代理商： | CY7C457 |
512 x 18, 1K x 18, and 2K x 18 Cascadable
Clocked FIFOs with Programmable Flags
CY7C455
CY7C456
CY7C457
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 1992 - Revised January 3, 1997
Features
High-speed, low-power, first-in first-out (FIFO)
memories
512 x 18 (CY7C455)
1,024 x 18 (CY7C456)
2,048 x 18 (CY7C457)
0.65 micron CMOS for optimum speed/power
High-speed 83-MHz operation (12 ns read/write cycle
time)
Low power — I
CC
=90 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL compatible
Retransmit function
Parity generation/checking
Output Enable (OE
)
pins
Independent read and write enable pins
Center power and ground pins for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
52-pin PLCC and 52-pin PQFP
Functional Description
The CY7C455, CY7C456, and CY7C457 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features include
Almost Full/Empty flags and generation/checking of parity.
These FIFOs provide solutions for a wide variety of data buff-
ering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
LogicBlockDiagram
Pin Configurations
c455-1
c455-2
PARITY
THREE–STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG/PARITY
PROGRAM
REGISTER
D
0 – 17
ENR
CKR
HF
E/F
PAFE/XO
Q
0 – 7
, Q
/PG1/PE1
Q
9– 16
, Q17/PG2/PE2
ENW
CKW
MR
FL/RT
XI
OE
RAM
ARRAY
512 x 18
1024 x 18
2048 x 18
1
Top View
PLCC
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5
4 3 2
52 51 50 49 48 47
E/F
ENW
CKW
XO/PAFE
HF
D
2
D
1
D
0
XI
Q
0
Q
1
Q
2
Q
3
D
13
D
14
D
15
D
16
D
17
FL/RT
MR
CKR
ENR
OE
Q
17
Q
16
Q
15
D
1
D
1
D
1
D
9
V
C
(
V
C
V
S
D
8
D
7
D
6
D
5
D
4
D
3
Q
4
Q
5
Q
6
Q
7
Q
8
/
V
S
V
S
(
Q
9
Q
1
Q
1
Q
1
Q
1
Q
1
RLOGIC
/PG2/PE2
7C455
7C456
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4831 | 2K x9 x2 Double Sync FIFOs(2K x9 x2 雙路同步先進先出) |
| CY7C4801 | 256 x9 x2 Double Sync FIFOs(256 x9 x2 雙路同步先進先出) |
| CY7C4811 | 512 x9 x2 Double Sync FIFOs(512 x9 x2 雙路同步先進先出) |
| CY7C4821 | 1K x9 x2 Double Sync FIFOs(1K x9 x2 雙路同步先進先出) |
| CY7C4851 | 8K x9 x2 Double Sync FIFOs(8K x9 x2 雙路同步先進先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C457 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C457-14JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C457-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C457-20JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C457-30JC | 制造商:Rochester Electronics LLC 功能描述:2K X 18 52 PIN CLOCKED FIFO W/ PRGM FLAGS - Bulk |
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