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參數(shù)資料
| 型號： | CY7C43684AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 3.3 16K的x36 x2雙向同步FIFO瓦特/總線匹配（3.3 16K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43684AV |
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CY7C43644AV
CY7C43664AV/CY7C43684AV
24
PRELIMINARY
Notes:
37. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
38. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
39. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition HIGH one CLKB cycle later than shown.
40. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
41. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.
42. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[39]
t
ENS
t
ENH
X1 Word in FIFO1
(X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
ENB
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[37, 38]
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[42]
t
ENS
t
ENH
X2 Word in FIFO2
(X2+1)Words in FIFO2
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[40, 41]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
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