參數(shù)資料
型號(hào)： CY7C43683
廠商： Cypress Semiconductor Corp.
英文描述： 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線匹配)
中文描述： 16K的x36單向同步FIFO瓦特/總線匹配（16K的x36單向同步先進(jìn)先出帶總線匹配）
文件頁(yè)數(shù)： 25/28頁(yè)
文件大?。?/td> 422K
代理商： CY7C43683
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
25
PRELIMINARY
..
Table 1. Flag Programming
SPM
FS1/SEN
FS0/SD
MRS1
/
MRS2
↑
↑
↑
↑
↑
↑
↑
↑
X and Y Registers
[38]
H
H
H
64
H
H
L
16
H
L
H
8
H
L
L
Parallel programming via Port A
L
H
L
Serial programming via SD
L
H
H
Reserved
L
L
H
Reserved
L
L
L
Reserved
Table 2. Port A Enable Function
CSA
W/RA
ENA
MBA
CLKA
A
0
–
35
Outputs
In high-impedance state
Port Function
H
X
X
X
X
None
L
H
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
Active, Mail2 register
None
L
L
H
L
Active, Mail2 register
None
L
L
L
H
Active, Mail2 register
None
L
L
H
H
Active, Mail2 register
Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB
W/RB
ENB
MBB
CLKB
B
0
–
35
Outputs
In high-impedance state
Port Function
H
X
X
X
X
None
L
L
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
L
H
L
In high-impedance state
None
L
L
H
H
In high-impedance state
Mail2 write
L
H
L
L
Active, FIFO output register
None
L
H
H
L
Active, FIFO output register
FIFO read
L
H
L
H
Active, Mail1 register
None
L
H
H
H
Active, Mail1 register
Mail1 read (set MBF1 HIGH)
Note:
38. X register holds the offset for AE; Y register holds the offset for AF.
相關(guān)PDF資料
PDF描述
CY7C43634 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進(jìn)先出 帶總線匹配)
CY7C43624 256 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(256 x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43644 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43664 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43684 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
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