參數(shù)資料
型號(hào): CY7C43683
廠商: Cypress Semiconductor Corp.
英文描述: 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線匹配)
中文描述: 16K的x36單向同步FIFO瓦特/總線匹配(16K的x36單向同步先進(jìn)先出帶總線匹配)
文件頁(yè)數(shù): 19/28頁(yè)
文件大?。?/td> 422K
代理商: CY7C43683
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
19
PRELIMINARY
Notes:
34. If Port B is configured for word size, data can be written to the Mail2 register using B
(B
are
don
t care
inputs). In this first case, A
0
will have
valid data (A
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B
0
8
(B
9
35
are
don
t care
inputs). In this second case, A
will have valid data (A
9
35
will be indeterminate).
35. Clocks are free-running in this case.
36. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
37. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B
0
35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[34]
FIFO Retransmit Timing
ENB
RT1
t
PRT
t
RTR
EF/FF
[35, 36, 37]
相關(guān)PDF資料
PDF描述
CY7C43634 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進(jìn)先出 帶總線匹配)
CY7C43624 256 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(256 x36 x2 雙向同步先進(jìn)先出帶總線匹配)
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CY7C43664 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43684 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
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