參數(shù)資料
型號(hào): CY7C43666AV-7AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: FIFO
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 4K X 36 BI-DIRECTIONAL FIFO, 6 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
文件頁數(shù): 30/40頁
文件大小: 644K
代理商: CY7C43666AV-7AC
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 30 of 40
Notes:
48. If Port B size is word or byte, t
is referenced to the rising CLKB edge that reads the last word or byte Write of the long word, respectively.
49. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
EN
t
ENH
t
A
LOW
HIGH
FIFO1 Full
LOW
HIGH
t
EN
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1
[49]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO1
Output Register
Next Word From FIFO1
To FIFO1
CLKB
CSB
MBB
RENB
EFB/ORB
B
0
17
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
[48]
LOW
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