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參數(shù)資料
| 型號： | CY7C43663 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 4K的x36單向同步FIFO瓦特/總線匹配（4K的x36單向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 422K |
| 代理商： | CY7C43663 |
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CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
8
PRELIMINARY
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH
1
1
2
ns
Hold Time, BE/FWFT after MRS1/MRS2 HIGH
1
1
2
ns
Hold Time, SPM after MRS1/MRS2 HIGH
Hold Time, FS0/SD after CLKA
↑
Hold Time, FS1/SEN after CLKA
↑
Hold Time, FS1/SEN HIGH after MRS1/MRS2
HIGH
Skew Time between CLKA
↑
and CLKB
↑
for EF/
OR and FF/IR
Skew Time between CLKA
↑
and CLKB
↑
for AE
and AF
Access Time, CLKA
↑
to A
0
–
35
and CLKB
↑
to
B
0
–
35
Propagation Delay Time, CLKA
↑
to FF/IR
Propagation Delay Time, CLKB
↑
to EF/OR
Propagation Delay Time, CLKB
↑
to AE
Propagation Delay Time, CLKA
↑
to AF
Propagation Delay Time, CLKA
↑
to MBF1 LOW or
MBF2 HIGH and CLKB
↑
to MBF2 LOW or MBF1
HIGH
Propagation Delay Time, CLKA
↑
to B
0
–
35[9]
and
CLKB
↑
to A
0
–
35[10]
Propagation Delay Time, MBA to A
0
–
35
Valid and
MBB to B
0
–
35
Valid
Propagation Delay Time, MRS1/MRS2 or PRS
LOW to AE LOW, AF HIGH, FF/IR LOW, EF/OR
LOW and MBF1/MBF2 HIGH
1
1
2
ns
0
0
0
ns
0
0
0
ns
0
1
2
ns
t
SKEW1[8]
5
5
7.5
ns
t
SKEW2[8]
7
8
12
ns
t
A
1
6
1
8
3
10
ns
t
WFF
t
REF
t
PAE
t
PAF
t
PMF
1
6
1
8
2
8
ns
1
6
1
8
1
8
ns
1
6
1
8
1
8
ns
1
6
1
8
1
8
ns
0
6
0
8
0
12
ns
t
PMR
1
7
2
11
3
12
ns
t
MDV
1
6
2
9
3
11
ns
t
RSF
1
6
1
10
1
15
ns
t
EN
Enable Time, CSA or W/RA LOW to A
0
–
35
Active
and CSB LOW and W/RB HIGH to B
0
–
35
Active
Disable Time, CSA or W/RA HIGH to A
0
–
35
at High
Impedance and CSB HIGH or W/RB LOW to B
0
–
35
at High Impedance
1
6
2
8
2
10
ns
t
DIS
1
5
1
6
1
8
ns
t
PRT
t
RTR
Notes:
8.
Retransmit Pulse Width
60
60
60
ns
Retransmit Recovery Time
90
90
90
ns
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
Writing data to the Mail1 register when the B
0
–
35
outputs are active and MBB is HIGH.
10. Writing data to the Mail2 register when the A
0
–
35
outputs are active and MBA is HIGH.
9.
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
CY7C43623/
33/43/63/83
–
7
CY7C43623/
33/43/63/83
–
10
CY7C43623/
33/43/63/83
–
15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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PDF描述 |
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| CY7C43624 | 256 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(256 x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43644 | 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43664 | 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
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