參數(shù)資料
型號(hào): CY7C4364
廠(chǎng)商: Cypress Semiconductor Corp.
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 3.3每1000 4K的16K的× 36 × 18 × 2三總線(xiàn)先進(jìn)先出
文件頁(yè)數(shù): 29/40頁(yè)
文件大?。?/td> 644K
代理商: CY7C4364
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 29 of 40
Notes:
46. If Port C size is word or byte, t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
47. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKC edge and rising CLKA edge is less than t
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
t
DH
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
t
EN
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1
[47]
CLKC
MBC
WENC
FFC/IRC
C
0
17
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A
0
35
[46]
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