參數(shù)資料
型號(hào): CY7C43646AV-7AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: FIFO
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 1K X 36 BI-DIRECTIONAL FIFO, 6 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
文件頁數(shù): 17/40頁
文件大?。?/td> 644K
代理商: CY7C43646AV-7AC
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 17 of 40
AC Test Loads and Waveforms (
10 and
15)
R1 = 330
Switching Characteristics
Over the Operating Range
AC Test Loads and Waveforms (
7)
3.0V
3.3V
OUTPUT
R2 = 680
C
L
= 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
3 ns
3 ns
ALL INPUT PULSES
[18]
3.0V
GND
90%
10%
90%
10%
3 ns
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0 = 50
Parameter
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
Description
7C43646/
66/86AV
7
Min.
7C43646/
66/86AV
10
Min.
7C43646/
66/86AV
15
Min.
Unit
MHz
ns
ns
ns
ns
ns
Max.
133
Max.
100
Max.
67
Clock Frequency, CLKA, CLKB, or CLKC
Clock Cycle Time, CLKA, CLKB, or CLKC
Pulse Duration, CLKA, CLKB, or CLKC HIGH
Pulse Duration, CLKA, CLKB, or CLKC LOW
Set-Up Time, A
0
35
before CLKA
,
and C
0
17
before CLKC
Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA
; RENB
and MBB before CLKB
,
and WENC and MBC before CLKC
Set-Up Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW
before CLKA
or CLKB
[19]
Set-Up Time, FS0 and FS1 before MRS1 and MRS2 HIGH
Set-Up Time, BE/FWFT before MRS1 and MRS2 HIGH
Set-Up Time, SPM before MRS1 and MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
Set-Up Time, FS1/SEN before CLKA
Set-Up Time, FWFT before CLKA
Hold Time, A
0
35
after CLKA
,
and C
0
17
after CLKC
Hold Time, CSA, W/RA, ENA, and MBA after CLKA
; RENB and
MBB after CLKB
,
and WENC and MBC after CLKC
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after
CLKA
or CLKB
[19]
7.5
3.5
3.5
3
3
10
4
4
4
4
15
6
6
5
5
t
RSTS
2.5
4
5
ns
t
FSS
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
t
ENH
5
5
5
3
3
0
0
0
7
7
7
4
4
0
0
0
7.5
7.5
7.5
5
5
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
t
RSTH
1
2
2
ns
Notes:
18. C
= 5 pF for t
.
19. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
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