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參數(shù)資料
| 型號： | CY7C4231 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2K x 9 Synchronous FIFOs(2Kx9同步先進先出（FIFO）) |
| 中文描述： | 2K × 9（2Kx9同步先進先出（FIFO）的同步FIFO的） |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 550K |
| 代理商： | CY7C4231 |
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document #: 38-06016 Rev. *C
Page 6 of 19
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device.
Figure 2
demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
Figure 2
). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
FF
FF
EF
EF
Write
CLOCK(WCLK)
Write
ENABLE1 (WEN1)
Write
ENABLE2/LOAD
(WEN2/LD)
PROGRAMMABLE (PAF)
FULLFLAG(FF)# 1
CY7C42X1
9
18
DATA IN (D)
RESET(RS)
9
RESET(RS)
Read CLOCK(RCLK)
Read ENABLE1 (REN1)
OUTPUT ENABLE(OE)
PROGRAMMABLE (PAE)
EMPTY FLAG(EF)#1
9
DATA OUT(Q)
9
18
Read Enable2 (REN2)
CY7C42X1
EMPTY FLAG(EF)#2
FULLFLAG(FF)# 2
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory
Used in a Width Expansion Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4251 | 8K x 9 Synchronous FIFOs(8Kx9同步先進先出（FIFO）) |
| CY7C4235-25ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225V-15AC | OSC 5V SMT 7X5 CMOS PROGRM |
| CY7C4425V-15ASC | OSC 5V SMT 7X5 CMOS PROGRM |
| CY7C4245V-15ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4231-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin TQFP |
| CY7C4231-15AXC | 功能描述:先進先出 2Kx9 IDT Compat SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4231-15JC | 制造商:Rochester Electronics LLC 功能描述:512X9 .300 //-CASCADEFIFO " - Bulk |
| CY7C4231-15JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC T/R 制造商:Rochester Electronics LLC 功能描述:2K X 9 32 PIN IDT COMPAT SYNCH FIFO - Bulk |
| CY7C4231-15JXC | 功能描述:先進先出 2Kx9 IDT Compat SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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