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參數(shù)資料
| 型號(hào)： | CY7C4211 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x 9 Synchronous FIFOs(512x9同步先進(jìn)先出（FIFO）) |
| 中文描述： | 512 × 9（512x9同步先進(jìn)先出（FIFO）的同步FIFO的） |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大小： | 550K |
| 代理商： | CY7C4211 |
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document #: 38-06016 Rev. *C
Page 5 of 19
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in
Table 1
or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the Read
and Write pointers.
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as
n
and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as
m
and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421. (64 – m), CY7C4201
(256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m),
CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251
(8K – m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 1. Writing the Offset Registers
LD
WEN
WCLK
[1]
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Table 2. Status Flags
Number of Words in FIFO
CY7C4201
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
CY7C4421
CY7C4211
0
1 to n
[2]
(n + 1) to 32
33 to (64 – (m + 1))
(64 – m)
[3]
to 63
64
0
1 to n
[2]
(n + 1) to 128
129 to (256 – (m + 1))
(256 – m)
[3]
to 255
256
0
1 to n
[2]
(n + 1) to 256
257 to (512 – (m + 1))
(512 – m)
[3]
to 511
512
Number of Words in FIFO
FF
PAF
PAE
EF
CY7C4221
CY7C4231
CY7C4241
CY7C4251
0
1 to n
[2]
0
1 to n
[2]
0
1 to n
[2]
0
1 to n
[2]
H
H
L
L
H
H
L
H
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
(n + 1) to 4096
H
H
H
H
513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
(1024 – m)
[3]
to 1023
(2048 – m)
[3]
to 2047
(4096 – m)
[3]
to 4095
H
H
H
H
(8192 – m)
[3]
to 8191
H
L
H
H
1024
2048
4096
8192
L
L
H
H
Notes:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of
RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4201 | 256 x 9 Synchronous FIFOs(256x9同步先進(jìn)先出（FIFO）) |
| CY7C4221 | 1K x 9 Synchronous FIFOs(1Kx9同步先進(jìn)先出（FIFO）) |
| CY7C4241 | 4K x 9 Synchronous FIFOs(4Kx9同步先進(jìn)先出（FIFO）) |
| CY7C4421 | 64× 9 Synchronous FIFOs(64×9同步先進(jìn)先出（FIFO）) |
| CY7C4231 | 2K x 9 Synchronous FIFOs(2Kx9同步先進(jìn)先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4211 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C421-10JC | 制造商:Rochester Electronics LLC 功能描述:512 X 9 28 PIN .300 PARALLEL-CASCADEABLEFIFO " - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C421-10JXC | 功能描述:IC ASYNC FIFO MEM 512X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C421-10JXCT | 功能描述:IC ASYNC FIFO MEM 512X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C421-10PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 28-Pin PDIP |
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