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參數(shù)資料
| 型號： | CY7C4201 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x 9 Synchronous FIFOs(256x9同步先進先出（FIFO）) |
| 中文描述： | 256 × 9（256x9同步先進先出（FIFO）的同步FIFO的） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 550K |
| 代理商： | CY7C4201 |
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document #: 38-06016 Rev. *C
Page 2 of 19
Selection Guide
-10
-15
-25
Unit
Maximum Frequency
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Set-up
3
4
6
ns
Minimum Data or Enable Hold
0.5
1
1
ns
Maximum Flag Delay
8
10
15
ns
Active Power Supply Current
Commercial
35
35
35
ICC1
Industrial
40
40
40
CY7C4421
CY7C4201
CY7C4211
CY7C4221
CY7C4231
CY7C4241
CY7C4251
Density
64 × 9
256 × 9
512 × 9
1K × 9
2K × 9
4K × 9
8K × 9
Pin Definitions
Pin
Name
I/O
Description
D
0–8
Q
0–8
WEN1
Data Inputs
I
Data Inputs for 9-bit Bus
Data Outputs
O
Data Outputs for 9-bit Bus
Write Enable 1
I
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD Dual
Mode Pin
Write Enable 2
I
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
Load
I
REN1, REN2
Read Enable
Inputs
I
Enables Device for Read Operation
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4221 | 1K x 9 Synchronous FIFOs(1Kx9同步先進先出（FIFO）) |
| CY7C4241 | 4K x 9 Synchronous FIFOs(4Kx9同步先進先出（FIFO）) |
| CY7C4421 | 64× 9 Synchronous FIFOs(64×9同步先進先出（FIFO）) |
| CY7C4231 | 2K x 9 Synchronous FIFOs(2Kx9同步先進先出（FIFO）) |
| CY7C4251 | 8K x 9 Synchronous FIFOs(8Kx9同步先進先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4201-10JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4201-15JC | 制造商:Rochester Electronics LLC 功能描述:256 X 9 32 PIN IDT COMPAT SYNCH FIFO - Bulk |
| CY7C4201-15JXC | 功能描述:IC SYNC FIFO MEM 256X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4201-15JXCT | 功能描述:IC SYNC FIFO MEM 256X9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C420125AC | 制造商:Cypress Semiconductor 功能描述: |
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