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參數(shù)資料
| 型號(hào)： | CY7C409A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64 x 9 Cascadable FIFO(64 x 9位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| 中文描述： | 64 × 9級(jí)聯(lián)的FIFO（64 × 9位級(jí)聯(lián)型先進(jìn)先出（FIFO）的） |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | CY7C409A |
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CY7C408A
CY7C409A
10
Figure 5. Depth and Width Expansion
[23,24,25,26,27]
Notes:
22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output.
24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until
the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for
one internal cycle (at least t
) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will
line up behind the first word and will not appear on the outputs until SO has been brought LOW.
26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW.
27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output
ready flags. This need is due to the variation of delays of the FIFOs
28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used.
29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring.
The complement of this holds when data is shifted out as a packet.
192x 27Configuration
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
COMPOSITE
OUTPUT READY
SHIFTOUT
MR
COMPOSITE
INPUT READY
SHIFTIN
C408A–21
HF/AFE
HF/AFE
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
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DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
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DI
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DI
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DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
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DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
SI
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
IR
MR
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PDF描述 |
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| CY7C408A | 64 x 8 Cascadable FIFO(64 x 8 位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C4205 | 256 x 18 Synchronous FIFOs(256 x 18 同步 先進(jìn)先出) |
| CY7C4225 | 1K x 18 Synchronous FIFOs(1K x 18 同步 先進(jìn)先出) |
| CY7C4215 | 512 x 18 Synchronous FIFOs(512 x 18 同步 先進(jìn)先出) |
| CY7C4235 | 2K x 18 Synchronous FIFOs(2K x 18 同步先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C409A-35DMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C409A35PC | 制造商:CYPRESS 功能描述:* |
| CY7C409A-35PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 9 28-Pin PDIP |
| CY7C419-１０AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 256 x 9 32-Pin TQFP |
| CY7C419-10JC | 功能描述:IC ASYN FIFO MEM 256X9 32-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433 |
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