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參數(shù)資料
| 型號： | CY7C408A-25LMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| 中文描述： | 64 X 8 OTHER FIFO, 23 ns, CQCC28 |
| 封裝： | LCC-28 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 344K |
| 代理商： | CY7C408A-25LMB |
CY7C408A
CY7C409A
9
Possible Minimum Pulse Width Violation at the Boundary
Conditions
If the handshaking signals IR and OR are not properly used to
generate the SI and SO signals, it is possible to violate the
minimum (effective) SI and SO positive pulse widths at the full
and empty boundaries.
Cascading the 7C408/9A-35 Above 25 MHz
First, the capacity of N cascaded FIFOs is decreased from N
×
64 to (N
×
63) + 1.
If cascaded FIFOs are to be operated with an external clock
rate greater than 25 MHz, the interface IR signal must be in-
verted before being fed back to the interface SO pin (Figure
3). Two things should be noted when this configuration is im-
plemented.
Secondly, the frequency at the cascade interface is less than
the 35 MHz rate at which the external clocks may operate.
Therefore, the first device has its data shifted in faster than it
is shifted out, and eventually this device becomes momentarily
full. When this occurs, the maximum sustainable external
clock frequency changes from 35 MHz to the cascade inter-
face frequency.
[28]
When data packets
[29]
are transmitted, this phenomenon does
not occur unless more than three FIFOs are depth cascaded.
For example, if two FIFOs are cascaded, a packet of 127 (=2
×
63 + 1) words may be shifted in at up to 35 MHz and then
the entire packet may be shifted out at up to 35 MHz.
Figure 2. Shifting Words Out.
C408A–18
SHIFTOUT
HF
AFE
64
63
FULL
56
55
54
30
9
8
7
32
31
1
EMPTY
Figure 3. Cascaded Configuration Above 25 MHz.
Figure 4. Cascaded Configuration at or below 25 MHz
[22,23,24,25,26]
.
C408A–19
IR
SI
SO
OR
B
IR
SI
SO
OR
A
IR
SI
SO
OR
C
IR
SI
D
IN
2
1
N
UPSTREAM
DOWNSTREAM
IR
X
SI
X
D
INX
SO
X
OR
X
D
OUTX
SO
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
OR
128x 9 Configuration
HF/AFE
SI
IR
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
MR
SO
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
8
OR
SI
IR
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
MR
OUTPUT READY
SHIFT OUT
SHIFT IN
INPUT READY
DATA IN
DATA OUT
MR
C408A–20
HF/AFE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C409A-25LMB | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C408A-25DMB | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C408A-35PC | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C408A-409A | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
| CY7C409A-25DMB | 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C408A25PC | 制造商:CYPRESS 功能描述:* |
| CY7C408A-25PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 8 28-Pin PDIP |
| CY7C408A-25VC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 8 28-Pin SOJ |
| CY7C408A35PC | 制造商:CYPRESS 功能描述:*NEW* |
| CY7C408A-35PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 8 28-Pin PDIP |
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