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參數(shù)資料
| 型號(hào)： | CY7C403 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64 x 4 Cascadable FIFO(64 x 4 位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| 中文描述： | 64 × 4級(jí)聯(lián)的FIFO（64 × 4位級(jí)聯(lián)型先進(jìn)先出（FIFO）的） |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大小： | 224K |
| 代理商： | CY7C403 |
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CY7C401/CY7C403
CY7C402/CY7C404
8
FIFO Expansion
[13, 14, 15, 16, 17]
Notes:
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.
However, OR will remain LOW, indicating data at the output is not valid.
14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW until
the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.
15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH
for one internal cycle (at least t
) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,
they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,
then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset
is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.
18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready
flags. This need is due to the variation of delays of the FIFOs.
SO
DO
0
DO
1
DO
2
DO
3
OR
SI
IR
DI
0
DI
1
DI
2
DI
3
MR
SO
DO
0
DO
1
DO
2
DO
3
OR
SI
IR
DI
0
DI
1
DI
2
DI
3
MR
OUTPUT READY
SHIFT OUT
SHIFT IN
INPUT READY
DATA IN
DATA OUT
MR
C401–16
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
COMPOSITE
OUTPUT READY
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SO
OR
DO
0
DO
1
DO
2
DO
3
SI
DI
0
DI
1
DI
2
DI
3
IR
MR
SHIFT OUT
MR
COMPOSITE
INPUT READY
SHIFT IN
C401–17
128 x 4 Application
[18]
192 x 12 Application
[19]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C403-10PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP |
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| CY7C408A-15VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C408A25DC | 制造商:CYPRESS 功能描述:* |
| CY7C408A25PC | 制造商:CYPRESS 功能描述:* |
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